Merge pull request #911 from slaclab/pre-release

Release Candidate v2.25.1

Author: ruck314

base/fifo/rtl/xilinx/FifoAlteraMfDummy.vhd renamed to base/fifo/rtl/dummy/FifoAlteraMfDummy.vhd

@@ -64,4 +64,7 @@ architecture mapping of FifoAlteraMf is
 
 begin
 
+   assert (false)
+      report "surf.base.fifo: FifoAlteraMf not supported" severity failure;
+
 end mapping;

base/fifo/rtl/altera/FifoXpmDummy.vhd renamed to base/fifo/rtl/dummy/FifoXpmDummy.vhd

@@ -64,4 +64,7 @@ architecture mapping of FifoXpm is
 
 begin
 
+   assert (false)
+      report "surf.base.fifo: FifoXpm not supported" severity failure;
+
 end mapping;

base/fifo/ruckus.tcl

@@ -2,9 +2,19 @@
 source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
 
 # Load Source Code
-loadSource -lib surf -dir "$::DIR_PATH/rtl"
-loadSource -lib surf -dir "$::DIR_PATH/rtl/xilinx"
-loadSource -lib surf -dir "$::DIR_PATH/rtl/inferred"
+loadSource -lib surf -dir  "$::DIR_PATH/rtl"
+loadSource -lib surf -dir  "$::DIR_PATH/rtl/inferred"
+loadSource -lib surf -path "$::DIR_PATH/rtl/dummy/FifoAlteraMfDummy.vhd"
 
 # Load Simulation
 loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb"
+
+# Case on the Vivado Version
+if { $::env(VIVADO_VERSION) < 2019.1 } {
+   # Load a dummy module
+   loadSource -lib surf -path "$::DIR_PATH/rtl/dummy/FifoXpmDummy.vhd"
+   puts "\n\nWARNING: surf.base.fifo.xpm requires Vivado 2019.1 (or later)\n\n"
+} else {
+   # Load the wrapper
+   loadSource -lib surf -path "$::DIR_PATH/rtl/xilinx/FifoXpm.vhd"
+}

python/surf/axi/_AxiVersion.py

@@ -69,7 +69,7 @@ def __init__(self, numUserConstants = 0, **kwargs):
         ))
 
         def parseUpTime(var,read):
-            seconds=var.dependencies[0].get(read)
+            seconds=var.dependencies[0].get(read=read)
             if seconds == 0xFFFFFFFF:
                 click.secho(f'Invalid {var.path} detected', fg='red')
                 return 'Invalid'
@@ -189,7 +189,7 @@ def UserRst():
             name         = 'GitHashShort',
             mode         = 'RO',
             dependencies = [self.GitHash],
-            linkedGet    = lambda read: f'{(self.GitHash.get(read) >> 132):07x}',
+            linkedGet    = lambda read: f'{(self.GitHash.get(read=read) >> 132):07x}',
         ))
 
         self.add(pr.RemoteVariable(
@@ -214,7 +214,7 @@ def UserRst():
         ))
 
         def parseBuildStamp(var,read):
-            buildStamp = var.dependencies[0].get(read)
+            buildStamp = var.dependencies[0].get(read=read)
             if buildStamp is None:
                 return ''
             else:

python/surf/devices/analog_devices/_Ad9249.py

@@ -394,7 +394,7 @@ def setDelay(var, value, write):
 
     @staticmethod
     def getDelay(var, read):
-        return var.dependencies[0].get(read)
+        return var.dependencies[0].get(read=read)
 
     def readBlocks(self, *, recurse=True, variable=None, checkEach=False, index=-1, **kwargs):
         """

xilinx/general/microblaze/bd/2021.1/MicroblazeBasicCore.tcl

@@ -88,7 +88,7 @@ if { ${design_name} eq "" } {
    set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
    set nRet 1
 } elseif { [get_files -quiet ${design_name}.bd] ne "" } {
-   # USE CASES: 
+   # USE CASES:
    #    6) Current opened design, has components, but diff names, design_name exists in project.
    #    7) No opened design, design_name exists in project.
 
@@ -125,7 +125,7 @@ set bCheckIPsPassed 1
 ##################################################################
 set bCheckIPs 1
 if { $bCheckIPs == 1 } {
-   set list_check_ips "\ 
+   set list_check_ips "\
 xilinx.com:ip:axi_gpio:2.0\
 xilinx.com:ip:axi_intc:4.1\
 xilinx.com:ip:axi_timer:2.0\