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Merge pull request #1002 from slaclab/pre-release
Release Candidate v2.34.2
2 parents 4ec94a5 + dad63e9 commit f9fea6d

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11 files changed

+400
-352
lines changed

11 files changed

+400
-352
lines changed

‎axi/axi-stream/rtl/AxiStreamFifoV2.vhd

Lines changed: 17 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -44,8 +44,8 @@ entity AxiStreamFifoV2 is
4444
FIFO_ADDR_WIDTH_G : integer range 4 to 48 := 9;
4545
FIFO_FIXED_THRESH_G : boolean := true;
4646
FIFO_PAUSE_THRESH_G : integer range 1 to (2**24) := 1;
47-
SYNTH_MODE_G : string := "inferred";
48-
MEMORY_TYPE_G : string := "block";
47+
SYNTH_MODE_G : string := "inferred";
48+
MEMORY_TYPE_G : string := "block";
4949

5050
-- Internal FIFO width select, "WIDE", "NARROW" or "CUSTOM"
5151
-- WIDE uses wider of slave / master. NARROW uses narrower.
@@ -159,9 +159,10 @@ architecture rtl of AxiStreamFifoV2 is
159159
signal fifoValidLast : sl;
160160
signal fifoInFrame : sl;
161161

162-
signal burstEn : sl;
163-
signal burstLast : sl;
164-
signal burstCnt : natural range 0 to VALID_THOLD_G := 0;
162+
signal burstEn : sl;
163+
signal burstLast : sl;
164+
signal burstCnt : natural range 0 to VALID_THOLD_G := 0;
165+
signal firstCycle : sl;
165166

166167
signal sideBand : Slv8Array(1 downto 0);
167168

@@ -188,13 +189,13 @@ begin
188189
READY_EN_G => SLAVE_READY_EN_G,
189190
SLAVE_AXI_CONFIG_G => SLAVE_AXI_CONFIG_G,
190191
MASTER_AXI_CONFIG_G => FIFO_CONFIG_C)
191-
port map (
192-
axisClk => sAxisClk,
193-
axisRst => sAxisRst,
194-
sAxisMaster => sAxisMaster,
195-
sAxisSlave => sAxisSlave,
196-
mAxisMaster => fifoWriteMaster,
197-
mAxisSlave => fifoWriteSlave);
192+
port map (
193+
axisClk => sAxisClk,
194+
axisRst => sAxisRst,
195+
sAxisMaster => sAxisMaster,
196+
sAxisSlave => sAxisSlave,
197+
mAxisMaster => fifoWriteMaster,
198+
mAxisSlave => fifoWriteSlave);
198199

199200
-------------------------
200201
-- FIFO
@@ -323,7 +324,9 @@ begin
323324
fifoInFrame <= '0' after TPD_G;
324325
burstEn <= '0' after TPD_G;
325326
burstLast <= '0' after TPD_G;
327+
firstCycle <= '1' after TPD_G;
326328
else
329+
firstCycle <= '0' after TPD_G;
327330
-- Check if for burst mode
328331
if (burstEn = '1') and (burstLast = '0') and (fifoRead = '1') then
329332
-- Increment the counter
@@ -335,7 +338,7 @@ begin
335338
burstEn <= '0' after TPD_G;
336339
end if;
337340
end if;
338-
if (fifoValidLast = '1') or ((fifoRdCount >= VALID_THOLD_G) and (burstEn = '0')) then
341+
if (fifoValidLast = '1') or ((fifoRdCount >= VALID_THOLD_G) and (burstEn = '0') and firstCycle = '0') then
339342
-- Set the flags
340343
burstEn <= '1' after TPD_G;
341344
burstLast <= fifoValidLast after TPD_G;
@@ -360,7 +363,7 @@ begin
360363
fifoValid <= fifoValidInt;
361364
end generate;
362365

363-
sideBand(0) <= resize(fifoReadUser, 8); -- mTLastTUser
366+
sideBand(0) <= resize(fifoReadUser, 8); -- mTLastTUser
364367

365368
-- Map output Signals
366369
fifoReadMaster <= toAxiStreamMaster (fifoDout, fifoValid, FIFO_CONFIG_C);

‎axi/axi-stream/rtl/AxiStreamMon.vhd

Lines changed: 13 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,7 @@ architecture rtl of AxiStreamMon is
8989
signal bwMax : slv(39 downto 0);
9090
signal bwMin : slv(39 downto 0);
9191

92+
signal frameRateReset : sl;
9293
signal frameRateUpdate : sl;
9394
signal frameRateSync : slv(31 downto 0);
9495
signal frameRateMaxSync : slv(31 downto 0);
@@ -99,6 +100,15 @@ architecture rtl of AxiStreamMon is
99100

100101
begin
101102

103+
104+
U_RstSync : entity surf.RstSync
105+
generic map (
106+
TPD_G => TPD_G)
107+
port map (
108+
clk => axisClk,
109+
asyncRst => statusRst,
110+
syncRst => frameRateReset);
111+
102112
U_packetRate : entity surf.SyncTrigRate
103113
generic map (
104114
TPD_G => TPD_G,
@@ -116,7 +126,7 @@ begin
116126
trigRateOutMin => frameRateMinSync,
117127
-- Clocks
118128
locClk => axisClk,
119-
locRst => axisRst,
129+
locRst => frameRateReset,
120130
refClk => axisClk,
121131
refRst => axisRst);
122132

@@ -265,7 +275,7 @@ begin
265275
WIDTH_G => 32)
266276
port map (
267277
-- ASYNC statistics reset
268-
rstStat => axisRst,
278+
rstStat => statusRst,
269279
-- Write Interface (wrClk domain)
270280
wrClk => axisClk,
271281
wrEn => r.sizeValid,
@@ -283,7 +293,7 @@ begin
283293
WIDTH_G => 40)
284294
port map (
285295
-- ASYNC statistics reset
286-
rstStat => axisRst,
296+
rstStat => statusRst,
287297
-- Write Interface (wrClk domain)
288298
wrClk => axisClk,
289299
wrEn => r.updated,

‎base/general/rtl/StdRtlPkg.vhd

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -169,6 +169,7 @@ package StdRtlPkg is
169169
-- pragma translate_on
170170

171171
-- Add more slv array sizes here as they become needed
172+
type Slv512Array is array (natural range <>) of slv(511 downto 0);
172173
type Slv256Array is array (natural range <>) of slv(255 downto 0);
173174
type Slv255Array is array (natural range <>) of slv(254 downto 0);
174175
type Slv254Array is array (natural range <>) of slv(253 downto 0);
@@ -427,6 +428,7 @@ package StdRtlPkg is
427428
type Slv1Array is array (natural range <>) of slv(0 downto 0);
428429

429430
-- Add more slv vector array sizes here as they become needed
431+
type Slv512VectorArray is array (natural range<>, natural range<>) of slv(511 downto 0);
430432
type Slv256VectorArray is array (natural range<>, natural range<>) of slv(255 downto 0);
431433
type Slv255VectorArray is array (natural range<>, natural range<>) of slv(254 downto 0);
432434
type Slv254VectorArray is array (natural range<>, natural range<>) of slv(253 downto 0);

‎protocols/clink/rtl/ClinkFraming.vhd

Lines changed: 53 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -121,7 +121,7 @@ begin
121121
v.portData.dv := '1';
122122
v.portData.fv := parData(0)(25);
123123

124-
-- 8-bit, cameraLink spec V2.0, page 16
124+
-- 8-bit/10-tap, cameraLink spec V2.0, page 23-25
125125
if chanConfig.dataMode = CDM_8BIT_C then
126126
v.portData.lv := parData(0)(24) and parData(1)(27) and parData(2)(27);
127127
v.portData.data(0) := parData(0)(7 downto 0);
@@ -137,46 +137,58 @@ begin
137137
v.portData.data(8) := parData(2)(18 downto 11);
138138
v.portData.data(9) := parData(2)(26 downto 19);
139139

140-
-- 10-bit, cameraLink spec V2.0, page 17
140+
-- 10-bit/8-tap, cameraLink spec V2.0, page 26-28
141141
elsif chanConfig.dataMode = CDM_10BIT_C then
142-
v.portData.lv := parData(0)(24) and parData(1)(24) and parData(2)(24);
143-
v.portData.data(0)(4 downto 0) := parData(0)(4 downto 0);
144-
v.portData.data(0)(5) := parData(0)(6);
145-
v.portData.data(0)(6) := parData(0)(27);
146-
v.portData.data(0)(7) := parData(0)(5);
147-
v.portData.data(1)(2 downto 0) := parData(0)(9 downto 7);
148-
v.portData.data(1)(5 downto 3) := parData(0)(14 downto 12);
149-
v.portData.data(1)(7 downto 6) := parData(0)(11 downto 10);
150-
v.portData.data(2)(0) := parData(0)(15);
151-
v.portData.data(2)(5 downto 1) := parData(0)(22 downto 18);
152-
v.portData.data(2)(7 downto 6) := parData(0)(17 downto 16);
153-
v.portData.data(3)(4 downto 0) := parData(1)(4 downto 0);
154-
v.portData.data(3)(5) := parData(1)(6);
155-
v.portData.data(3)(6) := parData(1)(27);
156-
v.portData.data(3)(7) := parData(1)(5);
157-
v.portData.data(4)(2 downto 0) := parData(1)(9 downto 7);
158-
v.portData.data(4)(5 downto 3) := parData(1)(14 downto 12);
159-
v.portData.data(4)(7 downto 6) := parData(1)(11 downto 10);
160-
v.portData.data(5)(0) := parData(1)(15);
161-
v.portData.data(5)(5 downto 1) := parData(1)(22 downto 18);
162-
v.portData.data(5)(7 downto 6) := parData(1)(17 downto 16);
163-
v.portData.data(6)(4 downto 0) := parData(2)(4 downto 0);
164-
v.portData.data(6)(5) := parData(2)(6);
165-
v.portData.data(6)(6) := parData(2)(27);
166-
v.portData.data(6)(7) := parData(2)(5);
167-
v.portData.data(7)(2 downto 0) := parData(2)(9 downto 7);
168-
v.portData.data(7)(5 downto 3) := parData(2)(14 downto 12);
169-
v.portData.data(7)(7 downto 6) := parData(2)(11 downto 10);
170-
v.portData.data(8)(0) := parData(0)(26);
171-
v.portData.data(8)(1) := parData(0)(23);
172-
v.portData.data(8)(3 downto 2) := parData(1)(26 downto 25);
173-
v.portData.data(8)(4) := parData(1)(23);
174-
v.portData.data(8)(5) := parData(2)(15);
175-
v.portData.data(8)(7 downto 6) := parData(2)(19 downto 18);
176-
v.portData.data(9)(2 downto 0) := parData(2)(22 downto 20);
177-
v.portData.data(9)(4 downto 3) := parData(2)(17 downto 16);
178-
v.portData.data(9)(6 downto 5) := parData(2)(26 downto 25);
179-
v.portData.data(9)(7) := parData(2)(23);
142+
v.portData.lv := parData(0)(24) and parData(1)(24) and parData(2)(24);
143+
144+
v.portData.data(0)(0) := parData(0)(26);
145+
v.portData.data(0)(1) := parData(0)(23);
146+
v.portData.data(0)(6 downto 2) := parData(0)(4 downto 0);
147+
v.portData.data(0)(7) := parData(0)(6);
148+
v.portData.data(1)(0) := parData(0)(27);
149+
v.portData.data(1)(1) := parData(0)(5);
150+
151+
v.portData.data(2)(1 downto 0) := parData(1)(26 downto 25);
152+
v.portData.data(2)(4 downto 2) := parData(0)(9 downto 7);
153+
v.portData.data(2)(7 downto 5) := parData(0)(14 downto 12);
154+
v.portData.data(3)(1 downto 0) := parData(0)(11 downto 10);
155+
156+
v.portData.data(4)(0) := parData(1)(23);
157+
v.portData.data(4)(1) := parData(2)(15);
158+
v.portData.data(4)(2) := parData(0)(15);
159+
v.portData.data(4)(7 downto 3) := parData(0)(22 downto 18);
160+
v.portData.data(5)(1 downto 0) := parData(0)(17 downto 16);
161+
162+
v.portData.data(6)(1 downto 0) := parData(2)(19 downto 18);
163+
v.portData.data(6)(6 downto 2) := parData(1)(4 downto 0);
164+
v.portData.data(6)(7) := parData(1)(6);
165+
v.portData.data(7)(0) := parData(1)(27);
166+
v.portData.data(7)(1) := parData(1)(5);
167+
168+
v.portData.data(8)(1 downto 0) := parData(2)(21 downto 20);
169+
v.portData.data(8)(4 downto 2) := parData(1)(9 downto 7);
170+
v.portData.data(8)(7 downto 5) := parData(1)(14 downto 12);
171+
v.portData.data(9)(1 downto 0) := parData(1)(11 downto 10);
172+
173+
v.portData.data(10)(0) := parData(2)(22);
174+
v.portData.data(10)(1) := parData(2)(16);
175+
v.portData.data(10)(2) := parData(1)(15);
176+
v.portData.data(10)(7 downto 3) := parData(1)(22 downto 18);
177+
v.portData.data(11)(1 downto 0) := parData(1)(17 downto 16);
178+
179+
v.portData.data(12)(0) := parData(2)(17);
180+
v.portData.data(12)(1) := parData(2)(25);
181+
v.portData.data(12)(6 downto 2) := parData(2)(4 downto 0);
182+
v.portData.data(12)(7) := parData(2)(6);
183+
v.portData.data(13)(0) := parData(2)(27);
184+
v.portData.data(13)(1) := parData(2)(5);
185+
186+
v.portData.data(14)(0) := parData(2)(26);
187+
v.portData.data(14)(1) := parData(2)(23);
188+
v.portData.data(14)(4 downto 2) := parData(2)(9 downto 7);
189+
v.portData.data(14)(7 downto 5) := parData(2)(14 downto 12);
190+
v.portData.data(15)(1 downto 0) := parData(2)(11 downto 10);
191+
180192
end if;
181193

182194
-- Base, Medium, Full Modes
@@ -328,7 +340,7 @@ begin
328340
when CDM_10BIT_C =>
329341
if chanConfig.linkMode = CLM_DECA_C then
330342
v.byteData := r.portData;
331-
v.bytes := 10;
343+
v.bytes := 16;
332344
else
333345
v.byteData.data(0) := r.portData.data(0); -- T1, DA[07:00]
334346
v.byteData.data(1)(1 downto 0) := r.portData.data(1)(1 downto 0); -- T1, DA[09:08]

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