Correcting moving average

modules/moving_average/moving_average.v

@@ -36,7 +36,7 @@ module moving_average  #(
     input rst,                      // synch reset              input           1
 
     // Config. Parameters
-    input [$clog2(BITS_ACUM-BITS_ADC)-1:0] k,   // k=log2(decimation_factor)
+    input [$clog2(BITS_ACUM-BITS_ADC):0] k,   // k=log2(decimation_factor)
 
     // Input samples
     input [BITS_ADC-1:0] sample_in,     // input value              input           BITS_ADC (def. 8)
@@ -60,10 +60,10 @@ module moving_average  #(
     //      MAX_DECIM_FACTOR = 1 << (BITS_ACUM-BITS_ADC);
     localparam BIT_DIFF = BITS_ACUM - BITS_ADC;
 
-    wire [BIT_DIFF-1:0] DF;
+    wire [BIT_DIFF:0] DF;
     wire [BITS_ACUM-1:0] sum_tmp;
 
-    reg [BIT_DIFF-1:0] count; // IDEALLY, WOULD BE ONE (1)
+    reg [BIT_DIFF:0] count;
     reg [BITS_ACUM-1:0] acum;
 
     // Decimation Factor = 2^k = 1 << k
@@ -76,30 +76,30 @@ module moving_average  #(
     // Carga DF en el contador y luego se resta. Mejor para cuando se cambia
     //  DF sobre la marcha, porque la comparación es contra una cte.
     always @( posedge(clk) ) begin
-        rdy_out <= 1'b0;
-        sample_out <= 0;
+        rdy_out     <= 1'b0;
+        sample_out  <= 0;
         if(count == 0) count <= 1;  //just in case everything goes to hell.
                                     // remove later...
         if ( rst == 1'b1 ) begin
-            acum <= 0;
-            count <= DF; // Starts from DF
+            acum    <= 0;
+            count   <= DF; // Starts from DF
         end else begin
             if(rdy_in == 1'b1) begin
                 if( count != 1 ) begin
-                    count <= count - 1;
-                    acum <= sum_tmp;
+                    count   <= count - 1;
+                    acum    <= sum_tmp;
                 end else begin
-                    acum <= 0;
+                    acum    <= 0;
                     //sample_out <= sum_tmp[BITS_ACUM-1:BIT_DIFF];
                     sample_out <= (sum_tmp >> k);
                     rdy_out <= 1'b1;
-                    count <= DF;
+                    count   <= DF;
                 end
             end
         end
     end
 
-    `ifdef COCOTB_SIM                                                        // COCOTB macro
+    `ifdef COCOTB_SIM       // COCOTB macro
         initial begin
             $dumpfile ("waveform.vcd");
             $dumpvars (0,moving_average);

modules/moving_average/test/moving_average.py

@@ -9,32 +9,35 @@ def nsTimer (t):
 
 class SI_MASTER:
     def __init__ ( self, clk, rst , data, rdy):
-        self.clk = clk
-        self.rst = rst
-        self.fifo = []
-        self.data = data
-        self.rdy = rdy
-
+        self.clk    = clk
+        self.rst    = rst
+        self.fifo   = []
+        self.data   = data
+        self.rdy    = rdy
+
+        self.data   <= 0
+        self.rdy    <= 0
+
     def write(self, value):
         self.fifo.append(value)
-    
+
     @cocotb.coroutine
     def driver(self):
         while True:
             if(len(self.fifo) > 0):
-                self.data <= self.fifo.pop(0)
-                self.rdy <= 1
+                self.data   <= self.fifo.pop(0)
+                self.rdy    <= 1
             yield RisingEdge(self.clk)
-            self.rdy <= 0
-    
+            self.rdy    <= 0
+
 class SI_SLAVE:
     def __init__ ( self, clk, rst , data, rdy):
-        self.clk = clk
-        self.rst = rst
-        self.fifo = []
-        self.data = data
-        self.rdy = rdy
-        
+        self.clk    = clk
+        self.rst    = rst
+        self.fifo   = []
+        self.data   = data
+        self.rdy    = rdy
+
     @cocotb.coroutine
     def monitor (self):
         while True:
@@ -53,38 +56,38 @@ def Reset (dut):
 
 @cocotb.test()
 def test (dut):
-    
-    k = 1
+
+    k = 4
     n = (1 << k)
     dut.k <= k
-    
+
     fifo_test = []
     acum = 0
-    
-    si_master = SI_MASTER( dut.clk, dut.rst , dut.sample_in, dut.rdy_in )
-    si_slave = SI_SLAVE( dut.clk, dut.rst , dut.sample_out, dut.rdy_out)
+
+    si_master   = SI_MASTER( dut.clk, dut.rst, dut.sample_in, dut.rdy_in )
+    si_slave    = SI_SLAVE( dut.clk, dut.rst, dut.sample_out, dut.rdy_out)
 
     cocotb.fork( Clock(dut.clk,10,units='ns').start() )
     yield Reset(dut)
 
+    print("n={}".format(n))
     for i in range(100):
-        aux = 10*(i+1)
+        aux = 10*(i+1) % 256
         si_master.write(aux)
 #        print "i%n=" + repr(i%n) + "  i=" + repr(i)
-        if(i % n == 0):
-            fifo_test.append(acum + aux)
-            acum <= 0
+        if((i+1) % n == 0):
+            fifo_test.append((acum + aux) >> k)
+            acum = 0
         else:
-            acum <= acum + aux
+            acum = acum + aux
 
     cocotb.fork( si_master.driver() )
     cocotb.fork( si_slave.monitor() )
-    
+
     for i in range(500): yield RisingEdge(dut.clk)
-    
+
     print repr(n)
     print "-------------------- CORRECT --------------------"
     print fifo_test
     print "-------------------- READ --------------------"
     print si_slave.fifo
-