Usage

Usage (Planned)

This page covers the usage of the FPGA device via I2C. It is relatively simple with the only complication being the large 32-bit registers on the FPGA. This require 4 data frames to read a single register, so full device reads can be quite large (32 data frames for all 8 registers!).

Address

The slave address is 0x2A

Control Register(s)

There are two control registers on the device:

• read_channels: This 8-bit register designates which of the 8 encoder channels to report when a read is requested.
• erase_channels: When a bit in this 8-bit register is set to 1, the corresponding encoder channel will reset its counter to zero. The erase_channel register then resets to zero once these actions are complete.

Setting Control Registers

On a write call, the first data frame will set the read_channel register. If a second data frame is sent by the master, it will be written to the erase_channels register.

Reading from the device

After a read call, the device will write the contents of read_channels to the first data frame. It will then sequentially write the four data frames, in big-endian order, of each encoder register with an enable flag in the read_channels register.

It is the responsibility of the master to read the correct number of data frames based off of the received read_channels value.