Verilator dpump fix

rtl/SRAM.vp

@@ -165,13 +165,14 @@ module `mname`
 
 //; } else { # SRAM_TYPE == 1PORT_DBLPUMP
 
+   // READ on negedge
    always @(negedge clk_i) begin                             // READ 1PORT_DBLPUMP
       $display("`$myname` FOO %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
       if (~ez_i & wz_i) begin
 
          // Double-pump SRAM reads and writes on alternate clock edges.
          //; if ($SRAM_TYPE eq "1PORT_DBLPUMP") {
-         rd_data_o = mem[addr_i];                         
+         rd_data_o <= mem[addr_i];                         
          //; }
          //;
          // READ INFO (historical)
@@ -182,9 +183,10 @@ module `mname`
       end
    end
 
+   // WRITE on negedge
    always @(posedge clk_i) begin                              // WRITE 1PORT_DBLPUMP
       if (~ez_i & ~wz_i) begin
-         mem[addr_i] = wr_data_i;
+         mem[addr_i] <= wr_data_i;
          $display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
          $display("%m %1d: Wrote   wr_data_i mem[%1d] <= %16x", $time, addr_i, wr_data_i);
          $display("`$myname` t5 %5d: Wrote(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, `ri("wr_data_i")`);

rtl/fftram.vp

@@ -473,15 +473,23 @@ module `mname`
    //;         $wz_value = "suppress_wz_i[$snum]";
    //;     }
    //;
+
+//; # Yet another terrible hack
+//; # Some configs work only w blocking assignments and others w non-blocking :(
+//; # $ass = "=";   # ver:  1port 2port ~dpump;  vcs  1port 2port dpump
+//; # $ass = "<=";  # ver: ~1port 2port  dpump;  vcs ~1port 2port dpump
+//; my $ass = ($SRAM_TYPE eq "TRUE_1PORT") ? "=" : "<=";
+
    always @ (`$wz_event`) begin
-      if (cycle_num == `$nbits_cycle_num`'b0) `${sram}`_wz = 1'b1; else
+      if (cycle_num == `$nbits_cycle_num`'b0) `${sram}`_wz `$ass` 1'b1; else
       if ( fft_started & (
    //;     my $i; for ($i=0; $i < ($nunits-1); $i++) {
    //;     print "         (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum ) |\n";
    //;     }
    //;     print "         (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum )\n";
    //;     print "      )) begin\n";
-   //;     print "         ${sram}_wz = $wz_value;\n";
+   //;     print "         ${sram}_wz $ass $wz_value ? 1 : 0;\n";
+
    //;     if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) {    # BOTF
           // \$display(\"FLOOF BOTF %1d okay want to write ${sram}\", \$time);
 
@@ -500,7 +508,7 @@ module `mname`
    //;     }
       end
       else begin
-         `${sram}`_wz = 1'b1;
+         `${sram}`_wz `$ass` 1'b1;
       end
    end
    //; }

test/test-regress.sh

@@ -2,36 +2,10 @@
 bn=$(basename $0)  # E.g. 'test-gold.sh'
 
 NOTES="
-------------------------------------------------------------------------
 At the end of a successful test suite it says '47/48 tests PASSED'.
 This is correct, b/c one test is SUPPOSED to fail on purpose.
 Is this a problem?
 
-------------------------------------------------------------------------
-VCS tests work :)
-
-    function filter { stdbuf -oL -eL awk '/^TR (PASS|FAIL)/{print}'; }
-    ../bin/golden_test.sh --python -sim vcs |& filter
-      TR PASS: 0 mismatched results --- 8 1 1port (vcs)
-      TR PASS: 0 mismatched results --- 8 2 1port (vcs)
-      TR PASS: 0 mismatched results --- 8 1 2port (vcs)
-
-    function filter { stdbuf -oL -eL awk '/^TR (PASS|FAIL)/{print}'; }
-    ../bin/golden_test.sh --python -sim vcs |& filter
-      TR PASS: 0 mismatched results --- 8 1 1port (vcs)
-      TR PASS: 0 mismatched results --- 8 2 1port (vcs)
-      TR PASS: 0 mismatched results --- 8 1 2port (vcs)
-
-------------------------------------------------------------------------
-Verilator only works for 2port configurations :(
-
-    function filter { stdbuf -oL -eL awk '/^TR (PASS|FAIL)/{print}'; }
-    ../bin/golden_test.sh --python -sim verilator |& filter
-    TR FAIL: 9 mismatched results --- 8 1 1port (verilator)
-    TR FAIL: 9 mismatched results --- 8 2 1port (verilator)
-    TR PASS: 0 mismatched results --- 8 1 2port (verilator)
-
-------------------------------------------------------------------------
 TODO:
   - Choose just ONE option, python or perl, and get rid of the other one.
 "
@@ -46,11 +20,11 @@ DESCRIPTION
   python model of the same FFT using the same inputs. 
 
 OPTIONS
-  $bn --python -sim vcs   # You need VCS installed on your system BUT
-  $bn --perl   -sim vcs   # works with all thre sram types 1port, 2port, dpump
+  $bn --python -sim vcs   # You need VCS installed on your system
+  $bn --perl   -sim vcs
 
-  $bn --python -sim ver   # This will install verilator for you if needed BUT
-  $bn --python -sim ver   # '-sim verilator' only works for 2-port srams :(
+  $bn --python -sim ver   # This will try to install verilator if it's missing
+  $bn --python -sim ver
 
   $bn --notes    # For more info
 "  
@@ -117,7 +91,7 @@ if [ "$is_verilator" ]; then
             exit 13
         fi
     fi
-    verilator_caveats; export SKIP_DPUMP=1
+    # verilator_caveats; export SKIP_DPUMP=1  # dpump works now maybe woohoo!
 fi
 
 # Run the regressions!
@@ -130,6 +104,6 @@ fi
         |& $nobuf tee test_results.log \
         |  $nobuf egrep 'PASS|FAIL|ERR| failure is allowed'
 
-    [ "$is_verilator" ] && verilator_caveats
+    # [ "$is_verilator" ] && verilator_caveats
     egrep '^FINAL RESULT.*PASS' test_results.log || exit 13
 )