perf(timer): unify idle to HLT and bump LAPIC tick to 1ms

[Enigamict]

Description

First, On QEMU, CPU threads sometimes spiked to 900–1400% host CPU.
A combination of short-period timers(100 µs)and busy-wait, creating an interrupt reprogramming loop so dense that hlt was rarely reached.

Next, Added the changes below

1. LAPIC timer period from 100 µs → 1 ms to prevent interrupt overruns that keep cores from idling.

With this change, CPU runaway no longer occurs, and the system runs stably on QEMU.

Related links

How was this PR tested?

Notes for reviewers

[Enigamict]

todo: Investigate a strategy to branch timer configuration between QEMU and physical machines, reflecting their markedly different timer behavior.

[Enigamict]

To handle differences between real hardware and virtualized environments, I implemented detection for KVM/QEMU and adjusted the local APIC timer period accordingly.
The CPU sleep subsystem sleep_cpu_no_std::init() and sleep_cpu_no_std::reset_wakeup_timer() now uses wakeup_interval() to perform keep-alive scheduling: 1 ms under KVM/QEMU and 100 µs on bare-metal hardware.
Note that this detection relies on x86_64 CPUID information, so this adaptive timing mechanism is currently limited to the x86_64 architecture.

[ytakano]

If us <= 1000, the main CPU will not wake up after us microseconds.

[Enigamict]

OK. Having CPUs remain in the HLT state indefinitely when a specific timeout is requested would be a more serious issue. Therefore, I’ll revert this part to the previous implementation that uses a busy-loop for short waits.