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SazzadSowmik / HiVeGen-Pipeline-Reproduction

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Reproduction of the HiVeGen (Hierarchical LLM-based Verilog Generation) pipeline from the paper "HiVeGen – Hierarchical LLM-based Verilog Generation for Scalable Chip Design" (arXiv:2412.05393).

llvm verilog systemverilog hardware-designs hdl verilog-hdl hierachical verilog-code hierachical-structure llm-based hivegen hierarchical-hardware-design demo-paper-implementation paper-demo hivegen-demo
  • Updated Nov 18, 2025
  • SystemVerilog

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