UART verification using UVM with functional coverage, scoreboard, and test scenarios, simulated on QuestaSim.
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Feb 26, 2025 - Verilog
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uvm-testbench
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UVM-based verification environment for RISC-V Bit Manipulation Unit (BMU) covering key BitManip instructions
riscv systemverilog risc-v systemverilog-hdl bitmanipulation uvm-verification bitmanip uvm-testbench
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Sep 16, 2025 - SystemVerilog
A Verilog RTL design of a 1x3 packet router with a complete UVM testbench for verification. Includes FIFO buffers, FSM control, assertions, coverage, and synthesis support.
coverage fsm assertions verilog vcs synthesis systemverilog hardware-designs fifo vlsi questasim uvm digital-design functional-verification rtl-design uvm-testbench packet-router
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Sep 3, 2025 - JavaScript
🚦 Build and verify a 1x3 packet router with modular Verilog RTL and a UVM-based environment for efficient functional testing and coverage.
coverage fsm assertions verilog vcs synthesis systemverilog hardware-designs fifo vlsi questasim uvm digital-design functional-verification rtl-design uvm-testbench packet-router
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Sep 25, 2025 - JavaScript
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