A Dual Core MIPS CPU. Feature 11 32-bit instructions, 8-bit datapath, Arbiter, MMU, and ROM. Verified using RAM module which encoded a Fibonacci program and via Randomized test bench.

Synthesizable Verilog I2C master controller for the Microchip MCP4725 12-bit DAC, targeting FPGA. Implements a 100 kHz I2C bus, 7-state FSM, and 4-byte write protocol to set analog output voltage via a 12-bit DAC code

Complete Verilog implementation to interface ADS1115 ADC with Xilinx Zynq FPGA over I2C – features continuous mode, AXI register map, UART hex output, and integrated debugging.

Verilog implementation of an incremental memory system and FPGA seat reservation system

Single-Port RAM Implementation

PS userspace XRT application for the VD100 MA Crossover AIE-ML pipeline. Drives mm2s/s2mm HLS kernels and mygraph via XRT 2025.2 on XCVE2302. Includes golden test vector validation and XRT lifecycle performance analysis.