Layout improvements: Voltage bias and overlap resolution in LayoutPipelineSolver #26
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…dded a test for bias and overlap resolution
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fix: robustly resolve all chip overlaps in OverlapResolutionSolver Deep clone chip placements to avoid mutation Iteratively push overlapping chips apart until no overlaps remain If overlaps persist, aggressively scatter chips and rerun resolution Throw error if overlaps remain after max attempts
ManbirS07
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Sep 15, 2025
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ManbirS07
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ManbirS07
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Tried to fix the overlapResolutionSolver file
Ran npm run format to format the code according to the requirements
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/claim #12
This PR improves schematic layout clarity and test reliability by:
Adding a VoltageBiasSolver that biases chips with positive voltage nets (VCC/VDD/V+) upward for conventional schematic readability.
Adding an OverlapResolutionSolver that detects and nudges apart overlapping chip placements using a bounding-box approach and chip sizes when available.
Integrating both phases into the LayoutPipelineSolver pipeline.
Adding targeted assertions to verify “no overlaps” and the presence of an upward bias for VCC/V* chips.
Key changes
VoltageBiasSolver.ts:
Scans netMap for positive-voltage nets and biases connected chips upward.
OverlapResolutionSolver:
Performs pairwise overlap checks and minimal nudging using chip sizes and ensures spacing via a minGap.
2 )Pipeline wiring
voltageBiasSolver added before packInnerPartitionsSolver.
overlapResolutionSolver added after partitionPackingSolver (operates on final layout).
onSolved hooks used only where data must be captured downstream.