The aim of this repository is to try to implement SpinalHDL designs from scratch as possible going from a very simple one (LED blinking) to a more complex one (SoC with VexRiscv processor).
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make all: translate spinalHDL to verilog, synthetize, place and route. -
make time: show timing critical path. -
make clean: clean up compilation result.
This design makes one board LED to blink with randomly choosen on / off time.
In this design I start to use a APB bus to set the LEDs state.
In this design I connect an UART to the APB bus to send "Hello, world!" message.
In this design I integrate a BMB bus and a SRAM memory. A simple state machine will be used to send the memory content by the UART.
Refer to the LICENSE file.