ARES II - The Second Anachronistic RISC Embedded System

A project to implement a RISC-V CPU and peripherals. Because who doesn't want their own microcontroller?

Name		Name	Last commit message	Last commit date
Latest commit History 17 Commits
.gitignore		.gitignore
Makefile		Makefile
README.md		README.md
alu.v		alu.v
alu_tb.v		alu_tb.v
cmp.v		cmp.v
cmp_tb.v		cmp_tb.v
cpu.v		cpu.v
make_rom.py		make_rom.py
make_vram.py		make_vram.py
muldiv.v		muldiv.v
muldiv_tb.v		muldiv_tb.v
pins.pcf		pins.pcf
ppu.v		ppu.v
ppu_tb.v		ppu_tb.v
ram.v		ram.v
regfile.v		regfile.v
regfile_tb.v		regfile_tb.v
rom.v		rom.v
run		run
test.c		test.c
test.s		test.s
test_alu.s		test_alu.s
test_br.s		test_br.s
test_c.s		test_c.s
test_interrupt.s		test_interrupt.s
test_jalr.s		test_jalr.s
test_jmp.s		test_jmp.s
top.v		top.v
top_tb.v		top_tb.v
vram.v		vram.v

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