Move emitRef from Verilog to backend#487
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da-steve101 wants to merge 5 commits intoucb-bar:masterfrom
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Removed seemily redundant nameAll as called further down; Not passing tests as emitRef is called twice in some situations; Valid code is generated but does not start at T0
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I've tried to incorporate these suggestions (and simplify naming - generate names once during nameAll()). Please check branch pr487. |
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I don't think T and C should have equivalence. Looking at src/test/resources/MultiClockSuite_Comp_1.v, this verilog is actually unsynthesizable as T0 is used for clock and temporary variable but passes the test. |
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There is interaction between this change and multi-word literals in the C++ backend. I think we need to visit all clients of emitIndex and verify consistent usage (possibly forcing everyone to use Backend.emitRef). |
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Can one of the admins verify this patch? |
Conflicts: src/main/scala/Backend.scala
Conflicts: src/main/scala/Backend.scala
Don't use T0 for both clock and wire.
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Currently not passing the tests as for some test cases are named twice and hence index does not start at 0.
Not sure where this is happening, but seems like it shouldn't be. Any suggestions on where to look?