[WIP] Fixing Subtraction CIN Bug

[loglav03]

Description

When doing a 4-bit input a and b subtraction to get a 5 bit output, we must compute as 2's complement = (1's complement + 1)
See as a + (1's comp. of b) + 1 = a + (2's comp. of b).

The subtraction carry chain was originally computing 2's complement as 1's complement (a + (1's comp. of b)). The reason for this is that when the original wide hard adder was split into a 1-bit adder chain, the head adder of the chain was supposed to seed the rest of the chain with a carry-in of 1. Instead it computed GND (0) + VCC (1) + GND (0), which gives a cout of 0, seeding the rest of the chain with a carry-in of 0, resulting in a + (1's comp. of b). This was fixed to compute VCC + VCC + GND, which seeds a carry-in of 1 to the rest of the chain.

There is also an additional adder added to the tail end of the chain. This adder takes in GND and VCC and CIN as inputs and is supposed to output the correct sign bit out[4]. This is currently broken in the code as I was having trouble connecting the correct output back to the original wide hard adder.

See the issue below for a diagram of the bug and further explanation.

Related Issue

#2266

How Has This Been Tested?

No in depth testing done yet as the code still needs some fixing up.

Types of changes

• [ x] Bug fix (change which fixes an issue)
• New feature (change which adds functionality)
• Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

• My change requires a change to the documentation
• I have updated the documentation accordingly
• I have added tests to cover my changes
• All new and existing tests passed

[loglav03]

@vaughnbetz - Opened this PR for the next person to take over the issue.