Mini Open Processor in Verilog (RISC-V ABI)

Project Overview

This project implements a mini processor in Verilog that follows the RISC-V ABI (Application Binary Interface). It is a simple and extensible processor design aimed at understanding processor architecture and instruction set design.

Project Files

• alu.v: Arithmetic and Logic Unit (ALU) implementation, supporting basic operations such as ADD, SUB, AND, OR, etc.
• control.v: Control unit for instruction decoding and generating control signals for the ALU and registers.
• registers.v: General-purpose registers for storing data during instruction execution.

Requirements

• Verilog for the processor implementation.
• Simulation tools (e.g., ModelSim, XSIM) to test the design.