CVA6 RISC-V CPU

CVA6 is a 6-stage, single-issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M, A and C extensions as specified in Volume I: User-Level ISA V 2.3 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore, it is compliant to the draft external debug spec 0.13. Official Repository

🚀 Getting Started

Clone the repository

git clone https://github.com/vlsi-lab/cva6
cd cva6
git submodule update --init --recursive

Pyhton Enviroment

Each user should create their own Conda environment from the provided lock file:

conda env create -f environment_lock.yml
conda activate cva6

That’s clean, self-contained, and clearly tied to your existing environment_lock.yml.

🧰 RISC-V Toolchain and Verilator Setup

Usually, it is strongly recommended to use the toolchain built with the provided scripts. However, to avoid redundant downloads and builds, you can use the shared prebuilt toolchain provided, modifying cva6/verif/sim/setup-env.sh file:

export RISCV="/software/riscv/riscv64-cva6"    
export VERILATOR_INSTALL_DIR="/software/cva6/verilator-v5.008"        ##@VLSI-Lab Server
export SPIKE_SRC_DIR="/software/cva6/riscv-isa-sim"                   ##@VLSI-Lab Server
export SPIKE_INSTALL_DIR="/software/spike/spike"                      ##@VLSI-Lab Server
export SPIKE_PATH="$SPIKE_INSTALL_DIR/bin"            

The shared toolchain is built from the official CVA6 scripts (util/toolchain-builder) and supports all required extensions. Users do not need to rebuild it locally unless they plan to modify or extend the toolchain itself.

Tests

To run a test using the core and the Verilator simulator, execute:

source tests/hello-world/hello_world.sh

Acknowledgements

Check out the acknowledgements.