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The C shift operators do not precisely match the associated ARM instructions: shifts of negative values or by negative amounts are undefined behavior in C, and GCC may substitute alternate instruction sequences when it can determine that the application is using UB.

Replace C shift operators with inline asm to ensure the lsll and asrl primitives always emit the indicated instruction.

This issue caused mis-compilation of the ARM cmsis-dsp code for arm_biquad_cascade_df1_32x64_q31:

https://github.com/ARM-software/CMSIS-DSP/pull/265

This has been submitted upstream to GCC:

https://gcc.gnu.org/pipermail/gcc-patches/2025-August/692431.html

The C shift operators do not precisely match the associated ARM
instructions: shifts of negative values or by negative amounts are
undefined behavior in C, and GCC may substitute alternate instruction
sequences when it can determine that the application is using UB.

Replace C shift operators with inline asm to ensure the lsll and asrl
primitives always emit the indicated instruction.

This issue caused mis-compilation of the ARM cmsis-dsp code for
arm_biquad_cascade_df1_32x64_q31:

	ARM-software/CMSIS-DSP#265

Signed-off-by: Keith Packard <keithp@keithp.com>
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