nxp/s32k3: add C40 internal flash driver + MCUboot flow for MR-CANHUBK3 #97401
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⛔ DNM label due to: 1 project with metadata changes, 4 blob changes and 1 impostor SHA Note: This message is automatically posted and updated by the Manifest GitHub Action. |
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| # Use Systick as system clock | ||
| CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=160000000 |
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must be set in soc Kconfig.defconfig and come from dts using dt function
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@nordicjm Same is defined in boards/nxp/mr_canhubk3/mr_canhubk3_defconfig, so I followed the same precedence
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Now you can fix 2 boards with one stone (commit)!
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soc/nxp/s32/s32k3/Kconfig.defconfig already has default value for this config -
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 2000000
This board defconfig overrides it
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@nordicjm .. Made the changes.. please check now
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move the fix commit before the board commit, so that the board doesn't have this line at all, as said https://docs.zephyrproject.org/latest/contribute/contributor_expectations.html#pr-requirements
No fixup or merge commits are allowed, see Contribution Workflow for more information.
| - hal | ||
| - name: hal_nxp | ||
| revision: 6d6ab91d5cc71c872353af1957d19f3d930df0fd | ||
| revision: 59a3b6c6ec1aa4ed11c2a4ba75f197f3b3a9c43d |
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you cannot include a manifest update after changes that need it
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@nordicjm .. I will remove it once my HAL PR gets merged, for now I need these changes to make the Twister cases pass.
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@sumitbatra-nxp What he is telling you is that your Zephyr side commit history has to be bisectable. You have commits in your history that are in the wrong order in that you have a commit using features that are not introduced until a later commit bringing in the HAL change.
You have to fix this now in your commit as we will not merge the HAL PR until everything is clean in your Zephyr side.
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@dleach02
Restored west.yml to the original hal_nxp revision and will wait for the HAL PR to merge before adding a manifest bump.
Once the HAL is merged I’ll re-order commits so the manifest bump comes before the driver changes.
Please let me know if there is still any gap in my understanding.
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Once the HAL is merged I’ll re-order commits so the manifest bump comes before the driver changes.
Do this even if the manifest is pointing to the unmerged hal_nxp pr. Then after the hal_nxp pr is merged, you only need to change in the manifest the pr to the merged sha. It will ease review.
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@nordicjm Changed the sequence of commits as requested
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Update hal_nxp SHA so Zephyr uses the revision that adds S32K3 C40 flash controller support. Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Add flash controller driver for the on-chip C40 flash controller The driver is backed by the MCUX C40 HAL and implements read/erase/program, page layout, and an optional protection policy that can lock well-known regions (IVT/MCUboot) derived from devicetree. Key details: - Selects FLASH_HAS_DRIVER_ENABLED / FLASH_HAS_EXPLICIT_ERASE / FLASH_HAS_PAGE_LAYOUT. - Runs erase/program from SRAM when XIP by relocating both the shim and the MCUX HAL source if CODE_DATA_RELOCATION_SRAM=y. - Optional protection pass at init (FLASH_MCUX_C40_APPLY_PROTECTION), which aligns windows to sector boundaries and applies lock/unlock using the HAL. This is useful on XIP systems to keep IVT/bootloader ranges read-only; can be disabled if a bootloader or security policy manages protection instead. Files: - drivers/flash/flash_mcux_c40.c (new) - drivers/flash/CMakeLists.txt (+zephyr_code_relocate when needed, Compliance fixes) - drivers/flash/Kconfig.mcux (enable flash driver, reloc & protection) - modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Introduce DT bindings for on-chip C40 flash and its controller and describe their corresponding nodes in nxp_s32k344_m7.dtsi. - Binding: dts/bindings/mtd/nxp,c40-flash.yaml Erase/write block sizes. - Binding: dts/bindings/flash_controller/nxp,c40-flash-controller.yaml Describe flash device (child) ranges - SoC nodes: With the new compatible and geometry properties. Keep status = "disabled" at the SoC level so boards opt-in. This prepares the platform for using Zephyr’s flash API / FLASH_MAP / MCUboot with internal code flash. Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Use devicetree to provide the system clock frequency for S32K3 instead of hardcoding it in board defconfigs. - Add clock-frequency to /cpus/cpu@0 in nxp_s32k344_m7.dtsi using DT_FREQ_M(160). - Define DT_SYSCLK_PATH and derive SYS_CLOCK_HW_CYCLES_PER_SEC from the sysclk node via dt_node_int_prop_int() when CORTEX_M_SYSTICK. - Remove CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC from mr_canhubk3 This keeps the clock configuration in a single SoC-level place, aligns S32K3 with other NXP Cortex-M SoCs, and ensures both the MCUboot and application builds share the same SYS_CLOCK_HW_CYCLES_PER_SEC. Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Emit the IVT section and IVT header only when XIP and the image is either a standalone XIP app or MCUboot itself. Do not emit the IVT when the Zephyr image is chain-loaded by MCUboot (BOOTLOADER_MCUBOOT=y). - linker.ld/sections.ld: place .ivt_header at IVT_HEADER only under XIP && (!BOOTLOADER_MCUBOOT || MCUBOOT). Provide __ivt_region_start/end symbols. - soc.c: guard IVT struct under the same condition and mark it 'used' so the linker keeps it when needed. - Kconfig.defconfig - Make the bootloader and the sign tool compatible with the vector table. This avoids populating 0x400000 IVT from the app image while retaining it for MCUboot or standalone XIP use-cases. Files: - soc/nxp/s32/s32k3/linker.ld - soc/nxp/s32/s32k3/sections.ld - soc/nxp/s32/s32k3/soc.c - soc/nxp/s32/s32k3/Kconfig.defconfig Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Add an mcuboot board variant under the S32K344 SoC in board.yml. New target is - mr_canhubk3/s32k344/mcuboot. This enables a single sysbuild invocation to build MCUboot and the application. Also make a common dtsi for all mr_canhubk3 board variants. Extend the board documentation with an “MCUboot (sysbuild)” section that: Shows one-command sysbuild to produce both MCUboot and app Documents signing via sysbuild (SB_CONFIG_BOOT_SIGNATURE_*), and where the signed artifacts are generated. Provides simple flashing instructions and a troubleshooting note about using a 1 KiB (0x400) image header and not emitting an IVT for chain-loaded apps. Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
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This series brings full internal-flash (C40) support and an end-to-end
MCUboot flow to the NXP MR-CANHUBK3 (S32K344) board.
What’s included
New driver: drivers/flash/flash_mcux_c40.c for the S32K3x C40 array
8 KiB erase / 8-byte write unit, page layout reporting
D-cache invalidation after mutating ops
Optional protection policy to lock IVT/MCUboot partitions at init
(CONFIG_SOC_FLASH_MCUX_C40_APPLY_PROTECTION)
Automatic relocation of driver + HAL to SRAM when XIP
Bindings & SoC DTSI: nxp,s32k3x-c40-flash.yaml and flash0 node in
nxp_s32k344_m7.dtsi (left status = "disabled" by default)
IVT/linker gating: place .ivt_header only when XIP and either
standalone app or MCUboot itself (avoid clashing with MCUboot image header
when chainloaded)
Board support: MCUboot partition layout & code-partition overlays for
mr_canhubk3, plus a small doc update
BUILD MCUBOOT AND FLASH_SHELL APP FOR CHAINLOAD
west build -p -b mr_canhubk3/s32k344/mcuboot --sysbuild -s zephyr/samples/drivers/flash_shell -d build/sys_mcuboot -- -DSB_CONFIG_BOOT_SIGNATURE_TYPE_RSA=y -DSB_CONFIG_BOOT_SIGNATURE_KEY_FILE="${PWD}/bootloader/mcuboot/root-rsa-2048.pem"
These changes need NXP_HAL PR -
zephyrproject-rtos/hal_nxp#618
For now I have disabled the flash0 node, till the time HAL changes are merged.