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@pvinci pvinci commented Nov 16, 2025

The current logic for Cortex-R5 FPU flags is inverted - it adds +nofp when FPU IS enabled, which is backwards.

Fixed logic:

  • If FPU is disabled: add +nofp suffix
  • If FPU is enabled without double precision: add +nofp.dp suffix
  • If FPU is enabled with double precision: use plain cortex-r5

This fixes builds for Cortex-R5F and other Cortex-R5F parts with VFPv3-D16.

The current logic for Cortex-R5 FPU flags is inverted - it adds +nofp
when FPU IS enabled, which is backwards.

Fixed logic:
- If FPU is disabled: add +nofp suffix
- If FPU is enabled without double precision: add +nofp.dp suffix
- If FPU is enabled with double precision: use plain cortex-r5

This fixes builds for Cortex-R5F and other Cortex-R5F parts with VFPv3-D16.

Signed-off-by: Paul Vinciguerra <pvinci@gmail.com>
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Hello @pvinci, and thank you very much for your first pull request to the Zephyr project!
Our Continuous Integration pipeline will execute a series of checks on your Pull Request commit messages and code, and you are expected to address any failures by updating the PR. Please take a look at our commit message guidelines to find out how to format your commit messages, and at our contribution workflow to understand how to update your Pull Request. If you haven't already, please make sure to review the project's Contributor Expectations and update (by amending and force-pushing the commits) your pull request if necessary.
If you are stuck or need help please join us on Discord and ask your question there. Additionally, you can escalate the review when applicable. 😊

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4 participants