zerorisc · LouisTheLuis · Sep 2, 2025
diff --git a/hw/ip/sfi_ctrl/data/sfi_ctrl.hjson b/hw/ip/sfi_ctrl/data/sfi_ctrl.hjson
@@ -0,0 +1,92 @@
+// Copyright zeroRISC Inc.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+  name:               "sfi_ctrl",
+  human_name:         "Secure Flash Interface Controller",
+  one_line_desc:      "Interfaces and manages a secure flash module (SFM) for safe and secure storage of boot code, keys, credentials and other sensitive information",
+  one_paragraph_desc: '''
+  //TODO: Write this.
+  '''
+
+  //TODO: Define this unique comportable IP identifier defined unders KNOWN_CIP_IDS in regtool
+  cip_id: "",
+  design_spec:    "../doc",
+  dv_doc:         "../doc/dv",
+  hw_checklist:   "
+  //TODO: Check hw_checklist with someone
+  ",
+  sw_checklist:   "
+  //TODO: Check sw_checklist with someone
+  ",
+  revisions: [
+    {
+      version: "1.0",
+      life_stage: "L1",
+      design_stage: "D0",
+      verification_stage: "V0"
+      commit_id: "
+      //TODO: Will be filled with the first PR
+      "
+    }
+  ],
+  clocking: [
+    { clock: "clk_i", reset: "rst_ni", primary: true },
+    { clock: "clock_otp_i", reset: "rst_otp_ni" }
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device", name: "core" },
+    { protocol: "tlul", direction: "device", name: "prim", hier_path: "u_eflash.u_flash.u_reg_top"},
+    { protocol: "tlul", direction: "device", name: "mem"}
+  ],
+  available_input_list: [
+    { name: "tck", desc: "jtag_clock" },
+    { name: "tms", desc: "jtag_tms" },
+    { name: "tdi", desc: "jtag input" }
+  ],
+  available_output_list: [
+    { name: "tdo", desc: "jtag output" }
+  ],
+  interrupt_list: [
+    // The first two status interrupts assert by default, since the FIFO is empty.
+    // This is captured in the Hjson via the `default` key so that automatically generated tests can incorporate this information.
+    { name: "prog_empty", type: "status", desc: "Program FIFO empty",            default: "1" },
+    { name: "prog_lvl",   type: "status", desc: "Program FIFO drained to level", default: "1" },
+    { name: "rd_full",    type: "status", desc: "Read FIFO full" },
+    { name: "rd_lvl",     type: "status", desc: "Read FIFO filled to level" },
+    { name: "op_done",    type: "event",  desc: "Operation complete" },
+    { name: "corr_err",   type: "event",  desc: "Correctable error encountered" }
+  ],
+
+  alert_list: [
+
+  ],
+
+  // Define flash_ctrl <-> flash_phy struct package
+  inter_signal_list: [
+
+  ],
+
+  countermeasures: [
+
+
+  ],
+  scan: "true",       // Enable `scanmode_i` port
+  scan_en: "true",    // Enable `scan_en_i` port
+  scan_reset: "true", // Enable `scan_rst_ni` port
+
+  param_list: [
+    // The reg parameters can be modified directly through top_*.hjson.
+    // The template will automatically propagate the appropriate values.
+
+    // Random netlist constants
+  ],
+
+  features: [
+
+  ],
+
+  regwidth: "32",
+
+  registers: {}
+}
diff --git a/hw/ip_templates/rstmgr/data/rstmgr.hjson.tpl b/hw/ip_templates/rstmgr/data/rstmgr.hjson.tpl
@@ -1,4 +1,5 @@
 // Copyright lowRISC contributors (OpenTitan project).
+// Copyright zeroRISC Inc.
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -167,18 +168,22 @@
     { name: "RSTMGR.RESET_INFO.CLEAR",
       desc: "Clear information about the causes of a reset."
     }
+% if with_alert_dump:
     { name: "RSTMGR.ALERT_INFO.CAPTURE",
       desc: "Capture alert crash dump information upon reset."
     }
     { name: "RSTMGR.ALERT_INFO.ENABLE",
       desc: "Enable capture of alert crash dump information."
     }
+% endif
+% if with_cpu_dump:
     { name: "RSTMGR.CPU_INFO.CAPTURE",
       desc: "Capture cpu crash dump information upon reset."
     }
     { name: "RSTMGR.CPU_INFO.ENABLE",
       desc: "Enable capture of cpu crash dump information."
     }
+% endif
     { name: "RSTMGR.ALERT_HANDLER.RESET_STATUS",
       desc: "Inform alert handler about reset enable status for each reset."
     }
@@ -226,6 +231,7 @@
       '''
     },
 
+% if with_alert_dump:
     { struct:  "alert_crashdump",
       type:    "uni",
       name:    "alert_dump",
@@ -236,6 +242,8 @@
       '''
     },
 
+% endif
+% if with_cpu_dump:
     { struct:  "cpu_crash_dump",
       type:    "uni",
       name:    "cpu_dump",
@@ -246,6 +254,7 @@
       '''
     },
 
+% endif
     { struct:  "mubi4",
       type:    "uni",
       name:    "sw_rst_req",
@@ -342,6 +351,7 @@
     },
 
     % for dump_src in crash_dump_srcs:
+      % if (dump_src == 'alert' and with_alert_dump) or (dump_src == 'cpu' and with_cpu_dump):
     { name: "${dump_src.upper()}_REGWEN",
       desc: "${dump_src.capitalize()} write enable",
       swaccess: "rw0c",
@@ -430,6 +440,7 @@
         },
       ]
     },
+      % endif
     % endfor
 
 

diff --git a/hw/ip_templates/rstmgr/data/rstmgr.tpldesc.hjson b/hw/ip_templates/rstmgr/data/rstmgr.tpldesc.hjson
@@ -1,4 +1,5 @@
 // Copyright lowRISC contributors (OpenTitan project).
+// Copyright zeroRISC Inc.
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
@@ -124,8 +125,14 @@
       default: {}
     }
     {
-      name: "with_alert_handler"
-      desc: "Generate outputs for a rstmgr that would connect to an alert handler"
+      name: "with_alert_dump"
+      desc: "Generate inputs and CSRs to capture an alert dump."
+      type: "bool"
+      default: "1"
+    }
+    {
+      name: "with_cpu_dump"
+      desc: "Generate inputs and CSRs to capture a cpu dump."
       type: "bool"
       default: "1"
     }

diff --git a/hw/ip_templates/rstmgr/doc/theory_of_operation.md.tpl b/hw/ip_templates/rstmgr/doc/theory_of_operation.md.tpl
@@ -134,13 +134,11 @@ The reset manager then checks as follows:
 
 - If all reset conditions are satisfied, wait for the reset release to gracefully complete the cycle.
 
-% if with_alert_handler:
 <%text>### Reset Indications for Alert Handler</%text>
 
 The alert handler needs to know the status of the various reset domains in the system to avoid false alert indications due to the ping mechanism.
 To that end, the reset manager outputs a 4bit MuBi signal for each reset domain that indicates whether its reset is active.
 For more information on this mechanism, see [alert handler documentation](../../alert_handler/doc/theory_of_operation.md#low-power-management-of-alert-channels).
-% endif
 
 <%text>## Design Details</%text>
 

diff --git a/hw/ip_templates/rstmgr/rstmgr.core.tpl b/hw/ip_templates/rstmgr/rstmgr.core.tpl
@@ -8,10 +8,12 @@ description: "Reset manager RTL"
 filesets:
   files_rtl:
     depend:
-% if with_alert_handler:
+% if with_alert_dump:
       - ${instance_vlnv("lowrisc:ip:alert_handler_pkg")}
 % endif
+% if with_cpu_dump:
       - lowrisc:ip:rv_core_ibex_pkg
+% endif
       - lowrisc:ip:tlul
       - lowrisc:prim:clock_mux2
       - lowrisc:prim:esc

diff --git a/hw/top_darjeeling/data/top_darjeeling.hjson b/hw/top_darjeeling/data/top_darjeeling.hjson
@@ -1,4 +1,5 @@
 // Copyright lowRISC contributors (OpenTitan project).
+// Copyright zeroRISC Inc.
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -1230,8 +1231,6 @@
       'pwrmgr_aon.boot_status'  : ['soc_dbg_ctrl.boot_status'],
       'keymgr_dpe.rom_digest'   : ['rom_ctrl0.keymgr_data',
                                    'rom_ctrl1.keymgr_data'],
-      'alert_handler.crashdump' : ['rstmgr_aon.alert_dump'],
-
       // DMA LSIO triggers
       'dma.lsio_trigger'        : ['soc_proxy.dma_lsio_trigger'],
       'i2c0.lsio_trigger'       : ['soc_proxy.i2c_lsio_trigger'],

diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/data/rstmgr.hjson b/hw/top_darjeeling/ip_autogen/rstmgr/data/rstmgr.hjson
@@ -1,4 +1,5 @@
 // Copyright lowRISC contributors (OpenTitan project).
+// Copyright zeroRISC Inc.
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 

diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/data/top_darjeeling_rstmgr.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/rstmgr/data/top_darjeeling_rstmgr.ipconfig.hjson
@@ -482,7 +482,8 @@
     ]
     rst_ni: lc_io_div4
     export_rsts: {}
-    with_alert_handler: true
+    with_alert_dump: true
+    with_cpu_dump: true
     topname: darjeeling
     uniquified_modules: {}
     module_instance_name: rstmgr

diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/data/rstmgr.hjson b/hw/top_earlgrey/ip_autogen/rstmgr/data/rstmgr.hjson
@@ -1,4 +1,5 @@
 // Copyright lowRISC contributors (OpenTitan project).
+// Copyright zeroRISC Inc.
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 

diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/data/top_earlgrey_rstmgr.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/rstmgr/data/top_earlgrey_rstmgr.ipconfig.hjson
@@ -690,7 +690,8 @@
     ]
     rst_ni: lc_io_div4
     export_rsts: {}
-    with_alert_handler: true
+    with_alert_dump: true
+    with_cpu_dump: true
     topname: earlgrey
     uniquified_modules: {}
     module_instance_name: rstmgr

diff --git a/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson b/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson
@@ -1949,17 +1949,6 @@
           top_signame: rstmgr_aon_rst_en
           index: -1
         }
-        {
-          name: alert_dump
-          desc: Alert handler crash dump information.
-          struct: alert_crashdump
-          package: alert_handler_pkg
-          type: uni
-          act: rcv
-          width: 1
-          inst_name: rstmgr_aon
-          index: -1
-        }
         {
           name: cpu_dump
           desc: Main processing element crash dump information.
@@ -5873,7 +5862,7 @@
               {
                 hart: 0x40410000
               }
-              size_byte: 0x80
+              size_byte: 0x40
             }
           ]
           xbar: false
@@ -10236,17 +10225,6 @@
         top_signame: rstmgr_aon_rst_en
         index: -1
       }
-      {
-        name: alert_dump
-        desc: Alert handler crash dump information.
-        struct: alert_crashdump
-        package: alert_handler_pkg
-        type: uni
-        act: rcv
-        width: 1
-        inst_name: rstmgr_aon
-        index: -1
-      }
       {
         name: cpu_dump
         desc: Main processing element crash dump information.

diff --git a/hw/top_englishbreakfast/dv/autogen/xbar_env_pkg__params.sv b/hw/top_englishbreakfast/dv/autogen/xbar_env_pkg__params.sv
@@ -62,7 +62,7 @@ tl_device_t xbar_devices[$] = '{
         '{32'h40400000, 32'h4040007f}
     }},
     '{"rstmgr_aon", '{
-        '{32'h40410000, 32'h4041007f}
+        '{32'h40410000, 32'h4041003f}
     }},
     '{"clkmgr_aon", '{
         '{32'h40420000, 32'h4042007f}

diff --git a/hw/top_englishbreakfast/dv/autogen/xbar_tgl_excl.cfg b/hw/top_englishbreakfast/dv/autogen/xbar_tgl_excl.cfg
@@ -80,7 +80,7 @@
 -node tb.dut*.u_pwrmgr_aon tl_*i.a_address[21:7]
 -node tb.dut*.u_pwrmgr_aon tl_*i.a_address[29:23]
 -node tb.dut*.u_pwrmgr_aon tl_*i.a_address[31:31]
--node tb.dut*.u_rstmgr_aon tl_*i.a_address[15:7]
+-node tb.dut*.u_rstmgr_aon tl_*i.a_address[15:6]
 -node tb.dut*.u_rstmgr_aon tl_*i.a_address[21:17]
 -node tb.dut*.u_rstmgr_aon tl_*i.a_address[29:23]
 -node tb.dut*.u_rstmgr_aon tl_*i.a_address[31:31]

diff --git a/hw/top_englishbreakfast/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_englishbreakfast/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
@@ -259,7 +259,7 @@
           {
             hart: 0x40410000
           }
-          size_byte: 0x80
+          size_byte: 0x40
         }
       ]
       xbar: false

diff --git a/hw/top_englishbreakfast/ip/xbar_peri/dv/autogen/xbar_cover.cfg b/hw/top_englishbreakfast/ip/xbar_peri/dv/autogen/xbar_cover.cfg
@@ -46,7 +46,7 @@
 -node tb.dut tl_pwrmgr_aon_o.a_address[21:7]
 -node tb.dut tl_pwrmgr_aon_o.a_address[29:23]
 -node tb.dut tl_pwrmgr_aon_o.a_address[31:31]
--node tb.dut tl_rstmgr_aon_o.a_address[15:7]
+-node tb.dut tl_rstmgr_aon_o.a_address[15:6]
 -node tb.dut tl_rstmgr_aon_o.a_address[21:17]
 -node tb.dut tl_rstmgr_aon_o.a_address[29:23]
 -node tb.dut tl_rstmgr_aon_o.a_address[31:31]

diff --git a/hw/top_englishbreakfast/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv b/hw/top_englishbreakfast/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
@@ -32,7 +32,7 @@ tl_device_t xbar_devices[$] = '{
         '{32'h40400000, 32'h4040007f}
     }},
     '{"rstmgr_aon", '{
-        '{32'h40410000, 32'h4041007f}
+        '{32'h40410000, 32'h4041003f}
     }},
     '{"clkmgr_aon", '{
         '{32'h40420000, 32'h4042007f}

diff --git a/hw/top_englishbreakfast/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv b/hw/top_englishbreakfast/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
@@ -27,7 +27,7 @@ package tl_peri_pkg;
   localparam logic [31:0] ADDR_MASK_RV_TIMER   = 32'h 000001ff;
   localparam logic [31:0] ADDR_MASK_USBDEV     = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_PWRMGR_AON = 32'h 0000007f;
-  localparam logic [31:0] ADDR_MASK_RSTMGR_AON = 32'h 0000007f;
+  localparam logic [31:0] ADDR_MASK_RSTMGR_AON = 32'h 0000003f;
   localparam logic [31:0] ADDR_MASK_CLKMGR_AON = 32'h 0000007f;
   localparam logic [31:0] ADDR_MASK_PINMUX_AON = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_AST        = 32'h 000003ff;