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[top,flash_macro] Extract prim_flash from flash_ctrl #77

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7 changes: 7 additions & 0 deletions BLOCKFILE
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@@ -1,3 +1,8 @@
# Copyright lowRISC contributors (OpenTitan project).
# Copyright zeroRISC Inc.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

# If a PR changes a file that matches a pattern in this file it will be blocked
# from merged by CI. The patterns as glob-like patterns matched using python
# fnmatch. In particular note there is no special handling for '/' so '*' can
Expand Down Expand Up @@ -41,6 +46,7 @@ hw/ip/aon_timer/rtl/*
hw/ip/csrng/rtl/*
hw/ip/edn/rtl/*
hw/ip/entropy_src/rtl/*
hw/ip/flash_macro_wrapper/rtl/*
hw/ip/hmac/rtl/*
hw/ip/i2c/rtl/*
hw/ip/keymgr/rtl/*
Expand Down Expand Up @@ -89,6 +95,7 @@ hw/ip/sysrst_ctrl/data/sysrst_ctrl.hjson
hw/ip/otbn/data/otbn.hjson
hw/ip/otp_macro/data/otp_macro.hjson
hw/ip/entropy_src/data/entropy_src.hjson
hw/ip/flash_macro_wrapper/data/flash_macro_wrapper.hjson
hw/ip/aes/data/aes.hjson
hw/ip/i2c/data/i2c.hjson
hw/top_earlgrey/data/otp/otp_ctrl.hjson
Expand Down
57 changes: 29 additions & 28 deletions hw/Makefile
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Expand Up @@ -19,34 +19,35 @@ endif
# The IPs listed here have their collateral generated by an invocation of
# regtool triggered here; those not in this list have their reg collateral
# generated by ipgen or topgen.
IPS ?= aes \
adc_ctrl \
aon_timer \
csrng \
dma \
edn \
entropy_src \
hmac \
i2c \
keymgr \
keymgr_dpe \
kmac \
lc_ctrl \
mbx \
otbn \
otp_macro \
pattgen \
pwm \
rom_ctrl \
rv_dm \
rv_timer \
sensor_ctrl \
soc_dbg_ctrl \
spi_device \
spi_host \
sram_ctrl \
sysrst_ctrl \
uart \
IPS ?= aes \
adc_ctrl \
aon_timer \
csrng \
dma \
edn \
entropy_src \
flash_macro_wrapper \
hmac \
i2c \
keymgr \
keymgr_dpe \
kmac \
lc_ctrl \
mbx \
otbn \
otp_macro \
pattgen \
pwm \
rom_ctrl \
rv_dm \
rv_timer \
sensor_ctrl \
soc_dbg_ctrl \
spi_device \
spi_host \
sram_ctrl \
sysrst_ctrl \
uart \
usbdev

TOPS ?= top_darjeeling top_earlgrey top_englishbreakfast
Expand Down
3 changes: 2 additions & 1 deletion hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_agent.core
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CAPI=2:
# Copyright lowRISC contributors (OpenTitan project).
# Copyright zeroRISC Inc.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:dv:flash_phy_prim_agent:0.1"
Expand All @@ -9,7 +10,7 @@ filesets:
depend:
- lowrisc:dv:dv_utils
- lowrisc:dv:dv_lib
- lowrisc:virtual_ip:flash_ctrl_top_specific_pkg
- lowrisc:virtual_ip:flash_phy_macro_pkg
files:
- flash_phy_prim_if.sv
- flash_phy_prim_agent_pkg.sv
Expand Down
13 changes: 6 additions & 7 deletions hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_agent_pkg.sv
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// Copyright lowRISC contributors (OpenTitan project).
// Copyright zeroRISC Inc.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

Expand All @@ -7,16 +8,14 @@ package flash_phy_prim_agent_pkg;
import uvm_pkg::*;
import dv_utils_pkg::*;
import dv_lib_pkg::*;
import flash_ctrl_top_specific_pkg::*;

import flash_phy_macro_pkg::DataWidth;
import flash_phy_macro_pkg::NumBanks;
import flash_phy_macro_pkg::flash_phy_macro_bank_req_t;
import flash_phy_macro_pkg::flash_phy_macro_bank_rsp_t;
// macro includes
`include "uvm_macros.svh"
`include "dv_macros.svh"

// parameters
localparam int unsigned PhyAddrW = flash_phy_pkg::BankAddrW;
localparam int unsigned PhyDataW = flash_phy_pkg::FullDataWidth;

// local types
// forward declare classes to allow typedefs below
typedef class flash_phy_prim_item;
Expand All @@ -26,7 +25,7 @@ package flash_phy_prim_agent_pkg;
typedef dv_base_sequencer #(.ITEM_T(flash_phy_prim_item),
.CFG_T (flash_phy_prim_agent_cfg)) flash_phy_prim_sequencer;

typedef logic [flash_phy_pkg::FullDataWidth-1:0] fdata_q_t[$];
typedef logic [DataWidth-1:0] fdata_q_t[$];

// functions

Expand Down
2 changes: 1 addition & 1 deletion hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_driver.sv
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Expand Up @@ -3,7 +3,7 @@
// SPDX-License-Identifier: Apache-2.0

class flash_phy_prim_driver extends dv_base_driver #(.ITEM_T(flash_phy_prim_item),
.CFG_T (flash_phy_prim_agent_cfg));
.CFG_T (flash_phy_prim_agent_cfg));
`uvm_component_utils(flash_phy_prim_driver)

// the base class provides the following handles for use:
Expand Down
13 changes: 8 additions & 5 deletions hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_if.sv
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// Copyright lowRISC contributors (OpenTitan project).
// Copyright zeroRISC Inc.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

interface flash_phy_prim_if (
input logic clk,
input logic rst_n
);
import flash_phy_pkg::*;
import flash_phy_macro_pkg::NumBanks;
import flash_phy_macro_pkg::flash_phy_macro_bank_req_t;
import flash_phy_macro_pkg::flash_phy_macro_bank_rsp_t;

flash_phy_prim_flash_req_t [NumBanks-1:0] req;
flash_phy_prim_flash_rsp_t [NumBanks-1:0] rsp;
flash_phy_macro_bank_req_t [NumBanks-1:0] req;
flash_phy_macro_bank_rsp_t [NumBanks-1:0] rsp;
// Inner read request / rdy
logic [NumBanks-1:0] rreq;
logic [NumBanks-1:0] rdy;

// Debug tab
flash_phy_prim_flash_req_t dreq0, dreq1;
flash_phy_prim_flash_rsp_t drsp0, drsp1;
flash_phy_macro_bank_req_t dreq0, dreq1;
flash_phy_macro_bank_rsp_t drsp0, drsp1;

assign dreq0 = req[0];
assign drsp0 = rsp[0];
Expand Down
5 changes: 3 additions & 2 deletions hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_item.sv
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// Copyright lowRISC contributors (OpenTitan project).
// Copyright zeroRISC Inc.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

Expand All @@ -7,8 +8,8 @@ class flash_phy_prim_item extends uvm_sequence_item;
`uvm_object_utils_begin(flash_phy_prim_item)
`uvm_object_utils_end

flash_phy_pkg::flash_phy_prim_flash_req_t req;
flash_phy_pkg::flash_phy_prim_flash_rsp_t rsp;
flash_phy_macro_bank_req_t req;
flash_phy_macro_bank_rsp_t rsp;

fdata_q_t fq;
`uvm_object_new
Expand Down
3 changes: 2 additions & 1 deletion hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_monitor.sv
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// Copyright lowRISC contributors (OpenTitan project).
// Copyright zeroRISC Inc.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

Expand All @@ -19,7 +20,7 @@ class flash_phy_prim_monitor extends dv_base_monitor #(
flash_phy_prim_item w_item[NumBanks];
flash_phy_prim_item r_item[NumBanks];
flash_phy_prim_item lm_item[NumBanks];
logic [PhyDataW-1:0] write_buffer[NumBanks][$];
logic [DataWidth-1:0] write_buffer[NumBanks][$];

`uvm_component_new

Expand Down
2 changes: 2 additions & 0 deletions hw/ip/BUILD
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# Copyright lowRISC contributors (OpenTitan project).
# Copyright zeroRISC Inc.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

Expand All @@ -21,6 +22,7 @@ filegroup(
"//hw/ip/dma:rtl_files",
"//hw/ip/edn:rtl_files",
"//hw/ip/entropy_src:rtl_files",
"//hw/ip/flash_macro_wrapper:rtl_files",
"//hw/ip/hmac:rtl_files",
"//hw/ip/i2c:rtl_files",
"//hw/ip/keymgr:rtl_files",
Expand Down
62 changes: 32 additions & 30 deletions hw/ip/README.md
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Expand Up @@ -2,36 +2,37 @@

<!-- BEGIN AUTOGEN Summary Table -->
<!-- Do NOT edit this section manually, it is generated by util/gen_doc_hw_summary_table.py. -->
| HW Block | Brief Summary |
|------------------|-----------------------------------------------------------------------------------------------------------------------------------|
| [`adc_ctrl`] | Low-power controller for a dual-channel ADC with filtering and debouncing capability |
| [`aes`] | AES encryption and decryption engine with SCA and FI countermeasures |
| [`aon_timer`] | Wakeup and watchdog timers running on a low-power, always-on clock |
| [`ascon`] | Ascon authenticated encryption and decryption engine |
| [`csrng`] | Takes entropy bits to produce cryptographically secure random numbers for consumption by hardware blocks and by software |
| [`dma`] | DMA Controller for the integrated OpenTitan. |
| [`edn`] | Distributes random numbers produced by CSRNG to hardware blocks |
| [`entropy_src`] | Filters and checks raw entropy bits from a random noise source and forwards them to CSRNG |
| [`hmac`] | Accelerator for SHA-2 256/384/512-based keyed HMAC and the hash function |
| [`i2c`] | I2C interface for host and device mode, supporting up to 1 Mbaud data rates |
| [`keymgr`] | Managing identities and root keys; shielding confidential assets from software; providing a key derivation interface for software |
| [`keymgr_dpe`] | Manage multiple DICE sessions in a DPE-compatible way |
| [`kmac`] | Accelerator for Keccak-based keyed hash message authentication code and SHA-3 hash functions; with SCA and FI countermeasures |
| [`lc_ctrl`] | Manages device life cycle states and transitions, and controls key manager, flash, OTP, and debug access |
| [`mbx`] | DOE mailbox for use as an integrated OpenTitan communication channel. |
| [`otbn`] | Programmable coprocessor for asymmetric cryptography with SCA and FI countermeasures |
| [`otp_macro`] | OTP macro simulation model and CSR block |
| [`pattgen`] | Transmission of short time-dependent data patterns on two clock-parallel output channels |
| [`rom_ctrl`] | Interfaces scrambled boot ROM with system bus and KMAC for initial health check after reset |
| [`rv_dm`] | Enables debug support for Ibex, access protected by life cycle |
| [`rv_timer`] | Memory-mapped timer unit implementing RISC-V mtime and mtimecmp registers |
| [`soc_dbg_ctrl`] | Control module to enable or disable debug access |
| [`spi_device`] | Serial peripheral interface supporting different device modes, suitable for bulk-load of data into and out of the chip |
| [`spi_host`] | Serial peripheral interface for host mode, suitable for interfacing external serial NOR flash devices |
| [`sram_ctrl`] | Interfacing on-chip SRAM blocks with system bus, supports lightweight scrambling, integrity and secure wipe |
| [`sysrst_ctrl`] | Manages board-level reset sequencing, interfaces reset and power manager |
| [`uart`] | Full duplex serial communication interface, supports bit rates of up to 1 Mbit/s |
| [`usbdev`] | USB 2.0 Full Speed device interface (12 Mbit/s) |
| HW Block | Brief Summary |
|-------------------------|-----------------------------------------------------------------------------------------------------------------------------------|
| [`adc_ctrl`] | Low-power controller for a dual-channel ADC with filtering and debouncing capability |
| [`aes`] | AES encryption and decryption engine with SCA and FI countermeasures |
| [`aon_timer`] | Wakeup and watchdog timers running on a low-power, always-on clock |
| [`ascon`] | Ascon authenticated encryption and decryption engine |
| [`csrng`] | Takes entropy bits to produce cryptographically secure random numbers for consumption by hardware blocks and by software |
| [`dma`] | DMA Controller for the integrated OpenTitan. |
| [`edn`] | Distributes random numbers produced by CSRNG to hardware blocks |
| [`entropy_src`] | Filters and checks raw entropy bits from a random noise source and forwards them to CSRNG |
| [`flash_macro_wrapper`] | FLASH macro simulation model and CSR block |
| [`hmac`] | Accelerator for SHA-2 256/384/512-based keyed HMAC and the hash function |
| [`i2c`] | I2C interface for host and device mode, supporting up to 1 Mbaud data rates |
| [`keymgr`] | Managing identities and root keys; shielding confidential assets from software; providing a key derivation interface for software |
| [`keymgr_dpe`] | Manage multiple DICE sessions in a DPE-compatible way |
| [`kmac`] | Accelerator for Keccak-based keyed hash message authentication code and SHA-3 hash functions; with SCA and FI countermeasures |
| [`lc_ctrl`] | Manages device life cycle states and transitions, and controls key manager, flash, OTP, and debug access |
| [`mbx`] | DOE mailbox for use as an integrated OpenTitan communication channel. |
| [`otbn`] | Programmable coprocessor for asymmetric cryptography with SCA and FI countermeasures |
| [`otp_macro`] | OTP macro simulation model and CSR block |
| [`pattgen`] | Transmission of short time-dependent data patterns on two clock-parallel output channels |
| [`rom_ctrl`] | Interfaces scrambled boot ROM with system bus and KMAC for initial health check after reset |
| [`rv_dm`] | Enables debug support for Ibex, access protected by life cycle |
| [`rv_timer`] | Memory-mapped timer unit implementing RISC-V mtime and mtimecmp registers |
| [`soc_dbg_ctrl`] | Control module to enable or disable debug access |
| [`spi_device`] | Serial peripheral interface supporting different device modes, suitable for bulk-load of data into and out of the chip |
| [`spi_host`] | Serial peripheral interface for host mode, suitable for interfacing external serial NOR flash devices |
| [`sram_ctrl`] | Interfacing on-chip SRAM blocks with system bus, supports lightweight scrambling, integrity and secure wipe |
| [`sysrst_ctrl`] | Manages board-level reset sequencing, interfaces reset and power manager |
| [`uart`] | Full duplex serial communication interface, supports bit rates of up to 1 Mbit/s |
| [`usbdev`] | USB 2.0 Full Speed device interface (12 Mbit/s) |
<!-- END AUTOGEN Summary Table -->

<!-- BEGIN AUTOGEN README Link Reference Definitions -->
Expand All @@ -44,6 +45,7 @@
[`dma`]: ./dma/README.md
[`edn`]: ./edn/README.md
[`entropy_src`]: ./entropy_src/README.md
[`flash_macro_wrapper`]: ./flash_macro_wrapper/README.md
[`hmac`]: ./hmac/README.md
[`i2c`]: ./i2c/README.md
[`keymgr`]: ./keymgr/README.md
Expand Down
14 changes: 14 additions & 0 deletions hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
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// Copyright lowRISC contributors (OpenTitan project).
// Copyright zeroRISC Inc.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
Expand Down Expand Up @@ -26,4 +27,17 @@ package flash_ctrl_pkg;
}
};

// Flash Program Operations Supported
typedef enum logic {
FlashProgNormal = 0,
FlashProgRepair = 1
} flash_prog_e;
parameter int ProgTypes = 2;

// Flash partition type
typedef enum logic {
FlashPartData = 1'b0,
FlashPartInfo = 1'b1
} flash_part_e;

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@LouisTheLuis LouisTheLuis Oct 16, 2025

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Why are these moved from flash_ctrl_top_specific_pkg.sv.tpl?

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@matutem matutem Oct 22, 2025

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Because it is needed in flash_macro_bank, which is not top-specific, to handle info pages in a special way. Even if there are no info pages the enum makes sense on its own, and the code that handles info pages will never be used.

endpackage : flash_ctrl_pkg
24 changes: 24 additions & 0 deletions hw/ip/flash_macro_wrapper/BUILD
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# Copyright zeroRISC Inc.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

package(default_visibility = ["//visibility:public"])

filegroup(
name = "rtl_files",
srcs = glob(
["**"],
exclude = [
"dv/**",
"doc/**",
"README.md",
],
) + [
"//hw/ip/flash_macro_wrapper/data:all_files",
],
)

filegroup(
name = "doc_files",
srcs = glob(["**/*.md"]),
)
16 changes: 16 additions & 0 deletions hw/ip/flash_macro_wrapper/README.md
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# Copyright zeroRISC Inc.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

# FLASH MACRO WRAPPER HWIP Technical Specification

# Overview

This document specifies the FLASH MACRO WRAPPER hardware IP functionality.
The FLASH MACRO WRAPPER is a comportable IP that wraps one or more flash bank macros.
This block is expected to be used in conjunction with a Flash Controller, and most of the features of the macro wrapper correspond to features of the controller.

## Features

The FLASH MACRO WRAPPER wraps flash macros, which can be either a simulation model, or vendor specific macro cells.
The wrapper features a CSR block for vendor specific operations.
11 changes: 11 additions & 0 deletions hw/ip/flash_macro_wrapper/data/BUILD
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# Copyright lowRISC contributors (OpenTitan project).
# Copyright zeroRISC Inc.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

package(default_visibility = ["//visibility:public"])

filegroup(
name = "all_files",
srcs = glob(["**"]),
)
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