sail: stage SSRGET/SSRSET/SSRSWAP

[zhoubot]

Stages Sail semantics for SSR system-register access per ISA manual operation pseudocode:

• SSRGET / SSRSET / SSRSWAP
• HL.SSRGET / HL.SSRSET

Adds minimal SSR backing storage for base IDs used in bring-up: TP/GP + LB*/LC*.
Other SSR IDs remain explicit unimplemented(...) until privilege + E_ISSR wiring is finalized.

Coverage: marks the above mnemonics as implemented; C.SSRGET and LSRGET remain missing (no SSRID remap / LSR spec).

implemented_forms -> 500.

[zhoubot]

Update (per doc analysis + your answers):

• Implemented C.SSRGET as direct low-bit SSRID domain (no remap): SSR_ID[4:0]=SSRID.
• Added trap_illegal_inst and trap_illegal_ssr stub: illegal SSR access raises TRAPNUM=ILLEGAL_INST(4), CAUSE=0, BI=0, TRAPARG0=PC/TPC.
• LSRGET remains unimplemented("lsrget") (engine-specific BARG access; spec TBD).

[zhoubot]

Update: marked unscaled immediate loads as implemented (semantics already present in execute.sail):

• LHI.U / LHUI.U / LWI.U / LWUI.U

Coverage refreshed (missing_mnemonics now 235).
Remaining non-V/HL missing are mainly: FPU ops, template ops (FENTRY/FEXIT/FRET.*, MCOPY/MSET, ESAVE/ERCOV), SSR conversions (SCVTF/UCVTF), XB, and LSRGET.