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Pull requests: LinxISA/linx-isa

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Pull requests list

v0.4: align kernel state, body semantics, and memory-space docs
#94 opened Mar 8, 2026 by zhoubot Loading…
Repin LinxCore for macro handoff IFU block
#88 opened Mar 6, 2026 by zhoubot Loading…
v0.3: document vector lane mask p + staged V.ADD/V.PSEL
#82 opened Mar 2, 2026 by zhoubot Loading…
sail: stage SSRGET/SSRSET/SSRSWAP
#81 opened Mar 2, 2026 by zhoubot Loading…
2
sail: complete remaining scalar load/store coverage
#80 opened Mar 2, 2026 by zhoubot Loading…
1
sail: cover LHI.U/LHUI.U/LWI.U/LWUI.U
#79 opened Mar 2, 2026 by zhoubot Loading…
sail: implement HL unscaled pre/post-index stores
#78 opened Mar 2, 2026 by zhoubot Loading…
sail: implement HL.ADDI/ADDIW/SUBI/SUBIW
#77 opened Mar 2, 2026 by zhoubot Loading…
sail: implement HL.CCAT/HL.CCATW
#76 opened Mar 2, 2026 by zhoubot Loading…
sail: implement HL.MIADD/HL.MISUB
#75 opened Mar 2, 2026 by zhoubot Loading…
sail: implement HL.BFI (wrap-around bitfield insert)
#74 opened Mar 2, 2026 by zhoubot Loading…
sail: implement HL arithmetic immediates
#73 opened Mar 2, 2026 by zhoubot Loading…
sail: stage SSR access semantics
#72 opened Mar 2, 2026 by zhoubot Loading…
Bump LinxCore for SPEC Stage-A images and xcheck flow
#64 opened Feb 28, 2026 by zhoubot Loading…
ProTip! Updated in the last three days: updated:>2026-03-12.