cpu/fe310: fixes for SW interrupt latency issues#12196
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kaspar030 merged 1 commit intoRIOT-OS:masterfrom Sep 17, 2019
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cpu/fe310: fixes for SW interrupt latency issues#12196kaspar030 merged 1 commit intoRIOT-OS:masterfrom
kaspar030 merged 1 commit intoRIOT-OS:masterfrom
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benpicco
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Area: cpu
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This looks like nice catch! 👍 |
kaspar030
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Sep 10, 2019
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Just FYI: #12109 has been merged, you need to rebase your PR against master :) |
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I'd say you can also squash. |
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I tested the changes on both HiFive1 and HiFive1B. Both work fine. |
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This fixes a bug that was present in the initial port to the new platform.
The fix looks good and was tested by the original author of the port.
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Fix for latency in invoking SW interrupt for context switching
Contribution description
FE310 uses a software interrupt to perform a context switch. This interrupt has a latency of 4-7 cycles, which can cause instructions to be executed after
thread_yield_higherleading to unpredictable results. The bug is similar to that found in #8897.Also added core panic support and fixed
cpu_switch_context_exitlogic.Testing procedure
Tested with all tests\thread_* apps
Issues/PRs references
Fixes: #12109
Fixes: #12110