Popular repositories Loading

1. Optimizing-RISC-V-for-High-Performance-Matrix-Multiplication-with-Custom-GEMM-Accelerator Optimizing-RISC-V-for-High-Performance-Matrix-Multiplication-with-Custom-GEMM-Accelerator Public

   SystemVerilog 2 2

2. Single-Cycle-RISCV-32I-Processor Single-Cycle-RISCV-32I-Processor Public

   Sytem verilog code for single cycle RISCV-32I processor.It supports all the base level instructions.

   SystemVerilog 1

3. CNN_Accelerator CNN_Accelerator Public

   C 1

4. RVVAutoVectorize RVVAutoVectorize Public

   C++ 1

5. Words_TimeStamps Words_TimeStamps Public

   Python project to get starting and ending timestamps of each word from audio

   Jupyter Notebook

6. RISC-V-Single-Cycle-Non-pipelined-Processor-Core RISC-V-Single-Cycle-Non-pipelined-Processor-Core Public

   This is Single cycle RISC_V processor code written in System Verilog to run on FPGAs.

   SystemVerilog