RISC-V-Single-Cycle-Processor-Core

This is Single cycle RISC_V processor code written in System Verilog to run on FPGAs.Some of the important Instructions of the RISC-V architecture is supported here. (a) R Type: ADD, SUB, OR, XOR, AND, SLT, SLTU. (b) I Type: ADDI, ORI, ANDI, SLTI, LW. (c) B Type: BEQ, BNE Simulation file is also included to run this Processor on simulator software like Modelsim.