Skip to content

Issues: chipsalliance/caliptra-ss

Beta
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

36 Open 140 Closed
36 Open 140 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

'generate fuse_ctrl partitions' questions
#493 opened May 29, 2025 by nelson-ou
5
simulation result have some problem for lsu axi address
#492 opened May 29, 2025 by cory-chiang
Integrating Caliptra SS and use Caliptra core in passive mode with external core
#491 opened May 29, 2025 by onishry
when caliptra_top axi burst = FIXED is used?
#490 opened May 29, 2025 by cory-chiang
MCI Ignores Volatile Unlock Approved bug Something isn't working
#487 opened May 27, 2025 by ekarabu
@ekarabu
1
Question about OTP ecc bits
#486 opened May 27, 2025 by DerekWangScaleflux
1
Question to fuse_ctrl access to OTP macro
#485 opened May 27, 2025 by DerekWangScaleflux
3
VCS Error in testbench file fc_lcc_tb_services
#484 opened May 23, 2025 by gyley1
Question regarding cptra_ss_clk settings.
#482 opened May 23, 2025 by KanaFuruhashi457
1
Open on OCP Streaming/Recovery interface
#481 opened May 22, 2025 by Alexandiz
@bharatpillilli
1
Open on JTAG connection for MCU
#479 opened May 22, 2025 by Alexandiz
[VeeR] Support for DCLS configuration parameters
#476 opened May 21, 2025 by moidx
8 tasks
[MCI/LCC] Add FIPS Zeroization Register 2.1 feature Approved enhancement New feature or request
#474 opened May 21, 2025 by clayton8
@clayton8
Question about LC_CTRL equivalent check (formality)
#458 opened May 15, 2025 by sukkyu25
@moidx
RDL issue - 2 2.1 feature Approved enhancement New feature or request
#452 opened May 14, 2025 by jchanga
@kgugala @nileshbpat
2
RDL issue enhancement New feature or request
#451 opened May 14, 2025 by jchanga
@nileshbpat
2
mismatch on Fuse map definition
#438 opened May 12, 2025 by Alexandiz
4
Debug and test in Manufacturing (MANUF) Life Cycle 2.1 feature Approved enhancement New feature or request
#436 opened May 12, 2025 by moshealon1
@ekarabu
How to generate header files for Caliptra SS address map
#435 opened May 12, 2025 by DerekWangScaleflux
@nileshbpat
4
WORKFLOW: Update pull request validation workflows with better file search rules enhancement New feature or request
#408 opened Apr 30, 2025 by calebofearth
@calebofearth
lc_ctrl prim_clock_mux2 question Further information is requested
#378 opened Apr 29, 2025 by Van-Jiang
@ekarabu @Nitsirks @andrea-caforio
1
Calitpra SS axi mem lint issue
#374 opened Apr 29, 2025 by ravithakurAMD
@calebofearth @ravithakurAMD
Caliptra SS streaming boot spec clarification documentation Improvements or additions to documentation
#358 opened Apr 27, 2025 by nileshbpat
@bharatpillilli @mhatrevi @nileshbpat
2
MCI SRAM offset configurability to adapt to Veer core region granularity of 256MB enhancement New feature or request
#337 opened Apr 25, 2025 by elecharo
@clayton8 @calebofearth
How to Simulation ?
#334 opened Apr 25, 2025 by Van-Jiang
1
ProTip! Follow long discussions with comments:>50.