Fix a lot of Scala compilation warnings

src/main/scala/amba/axi4/Fragmenter.scala

@@ -78,7 +78,7 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
 
         // We don't care about illegal addresses; bursts or no bursts... whatever circuit is simpler (AXI4ToTL will fix it)
         // !!! think about this more -- what if illegal?
-        val sizes1 = (supportedSizes1 zip slave.slaves.map(_.address)).filter(_._1 >= 0).groupBy(_._1).mapValues(_.flatMap(_._2))
+        val sizes1 = (supportedSizes1 zip slave.slaves.map(_.address)).filter(_._1 >= 0).groupBy(_._1).view.mapValues(_.flatMap(_._2)).toMap
         val reductionMask = AddressDecoder(sizes1.values.toList)
         val support1 = Mux1H(sizes1.toList.map { case (v, a) => // maximum supported size-1 based on target address
           (AddressSet.unify(a.map(_.widen(~reductionMask)).distinct).map(_.contains(addr)).reduce(_||_), v.U)

src/main/scala/amba/axi4/IdIndexer.scala

@@ -54,7 +54,7 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
       val field = if (bits > 0) Seq(AXI4ExtraIdField(bits)) else Nil
       mp.copy(
         echoFields = field ++ mp.echoFields,
-        masters    = masters.zip(finalNameStrings).map { case (m, n) => m.copy(name = n) })
+        masters    = masters.zip(finalNameStrings).map { case (m, n) => m.copy(name = n) }.toIndexedSeq)
     },
     slaveFn = { sp => sp
     })

src/main/scala/devices/debug/Debug.scala

@@ -1703,7 +1703,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
           flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true))}
         }),
       ROMBASE       -> RegFieldGroup("debug_rom", Some("Debug ROM"),
-        (if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).zipWithIndex.map{case (x, i) =>
+        (if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).toIndexedSeq.zipWithIndex.map{case (x, i) =>
           RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))})
     )
 

src/main/scala/devices/tilelink/BootROM.scala

@@ -99,7 +99,7 @@ object BootROM {
     }
 
     val bootrom = bootROMDomainWrapper {
-      LazyModule(new TLROM(params.address, params.size, contents, true, tlbus.beatBytes))
+      LazyModule(new TLROM(params.address, params.size, contents.toIndexedSeq, true, tlbus.beatBytes))
     }
 
     bootrom.node := tlbus.coupleTo(params.name){ TLFragmenter(tlbus, Some(params.name)) := _ }

src/main/scala/devices/tilelink/BusBypass.scala

@@ -4,7 +4,10 @@ package freechips.rocketchip.devices.tilelink
 
 import chisel3._
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
+import org.chipsalliance.diplomacy.ValName
+import org.chipsalliance.diplomacy.lazymodule._
+import org.chipsalliance.diplomacy.nodes.NodeHandle
+import freechips.rocketchip.diplomacy.{AddressSet, RegionType}
 import freechips.rocketchip.tilelink._
 
 abstract class TLBusBypassBase(beatBytes: Int, deadlock: Boolean = false, bufferError: Boolean = true, maxAtomic: Int = 16, maxTransfer: Int = 4096)

src/main/scala/devices/tilelink/Deadlock.scala

@@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink
 
 import chisel3._
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
+import org.chipsalliance.diplomacy.lazymodule._
 import freechips.rocketchip.resources.{SimpleDevice}
 
 /** Adds a /dev/null slave that does not raise ready for any incoming traffic.

src/main/scala/diplomacy/AddressDecoder.scala

@@ -12,8 +12,9 @@ object AddressDecoder
   type Partitions = Seq[Partition]
 
   val addressOrder = Ordering.ordered[AddressSet]
-  val portOrder = Ordering.Iterable(addressOrder)
-  val partitionOrder = Ordering.Iterable(portOrder)
+  import Ordering.Implicits._
+  val portOrder = Ordering[Seq[AddressSet]]
+  val partitionOrder = Ordering[Seq[Seq[AddressSet]]]
 
   // Find the minimum subset of bits needed to disambiguate port addresses.
   // ie: inspecting only the bits in the output, you can look at an address
@@ -126,7 +127,7 @@ object AddressDecoder
           println("  For bit %x, %s".format(bit, score.toString))
         (score, bit, result)
       }
-      val (bestScore, bestBit, bestPartitions) = candidates.min(Ordering.by[(Seq[Int], BigInt, Partitions), Iterable[Int]](_._1.toIterable))
+      val (bestScore, bestBit, bestPartitions) = candidates.min(Ordering.by[(Seq[Int], BigInt, Partitions), Seq[Int]](_._1))
       if (debug) println("=> Selected bit 0x%x".format(bestBit))
       bestBit +: recurse(bestPartitions, bits.filter(_ != bestBit))
     }

src/main/scala/diplomacy/Main.scala

@@ -5,7 +5,7 @@ import chisel3.stage.ChiselGeneratorAnnotation
 import chisel3.stage.phases.{Elaborate, Convert}
 import firrtl.AnnotationSeq
 import firrtl.options.TargetDirAnnotation
-import freechips.rocketchip.diplomacy.LazyModule
+import org.chipsalliance.diplomacy.lazymodule.LazyModule
 import org.chipsalliance.cde.config.{Config, Parameters}
 import mainargs._
 
@@ -22,7 +22,7 @@ object Main {
         .getConstructor(classOf[Parameters])
         .newInstance(new Config(config.foldRight(Parameters.empty) {
           case (currentName, config) =>
-            val currentConfig = Class.forName(currentName).newInstance.asInstanceOf[Config]
+            val currentConfig = Class.forName(currentName).getDeclaredConstructor().newInstance().asInstanceOf[Config]
             currentConfig ++ config
         })) match {
           case m: RawModule => m
@@ -51,6 +51,6 @@ object Main {
     freechips.rocketchip.util.ElaborationArtefacts.files.foreach{ case (ext, contents) => os.write.over(os.Path(dir) / s"${config.mkString("_")}.${ext}", contents()) }
   }
 
-  def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args)
+  def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args.toIndexedSeq)
 }
 

src/main/scala/diplomacy/Parameters.scala

@@ -2,6 +2,8 @@
 
 package freechips.rocketchip.diplomacy
 
+import scala.language.implicitConversions
+
 import chisel3._
 import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
 import freechips.rocketchip.util.ShiftQueue
@@ -30,8 +32,8 @@ case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
   require (start <= end, "Id ranges cannot be negative.")
 
   def compare(x: IdRange) = {
-    val primary   = (this.start - x.start).signum
-    val secondary = (x.end - this.end).signum
+    val primary   = (this.start - x.start).sign
+    val secondary = (x.end - this.end).sign
     if (primary != 0) primary else secondary
   }
 
@@ -119,7 +121,7 @@ object TransferSizes {
   def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
   def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
 
-  implicit def asBool(x: TransferSizes) = !x.none
+  implicit def asBool(x: TransferSizes): Boolean = !x.none
 }
 
 // AddressSets specify the address space managed by the manager

src/main/scala/diplomacy/package.scala

@@ -59,7 +59,7 @@ package object diplomacy {
   @deprecated("Diplomacy has been split to a standalone library", "rocketchip 2.0.0")
   def ValName(value:                String)          = _root_.org.chipsalliance.diplomacy.ValName(value)
   @deprecated("Diplomacy has been split to a standalone library", "rocketchip 2.0.0")
-  implicit def SourcecodeNameExt(x: sourcecode.Name) = _root_.org.chipsalliance.diplomacy.SourcecodeNameExt(x)
+  implicit def SourcecodeNameExt(x: sourcecode.Name): _root_.org.chipsalliance.diplomacy.SourcecodeNameExt = _root_.org.chipsalliance.diplomacy.SourcecodeNameExt(x)
 
 // LazyModule.scala
   @deprecated("Diplomacy has been split to a standalone library", "rocketchip 2.0.0")

src/main/scala/groundtest/Configs.scala

@@ -42,7 +42,7 @@ class WithTraceGen(
   wordBits: Int = 32
 ) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => {
-    val prev = up(TilesLocated(InSubsystem), site)
+    val prev = up(TilesLocated(InSubsystem))
     val idOffset = up(NumTiles)
     val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
     params.zipWithIndex.map { case (dcp, i) =>

src/main/scala/interrupts/Parameters.scala

@@ -2,6 +2,8 @@
 
 package freechips.rocketchip.interrupts
 
+import scala.language.implicitConversions
+
 import chisel3.experimental.SourceInfo
 
 import org.chipsalliance.cde.config._

src/main/scala/interrupts/package.scala

@@ -20,15 +20,15 @@ package object interrupts
   type IntSyncNode = SimpleNodeHandle[IntSourcePortParameters, IntSinkPortParameters, IntEdge, SyncInterrupts]
 
   implicit class IntClockDomainCrossing(private val x: HasClockDomainCrossing) extends AnyVal {
-    def crossIn (n: IntInwardNode) (implicit valName: ValName) = IntInwardClockCrossingHelper(valName.name, x, n)
-    def crossOut(n: IntOutwardNode)(implicit valName: ValName) = IntOutwardClockCrossingHelper(valName.name, x, n)
+    def crossIn (n: IntInwardNode) (implicit valName: ValName) = IntInwardClockCrossingHelper(valName.value, x, n)
+    def crossOut(n: IntOutwardNode)(implicit valName: ValName) = IntOutwardClockCrossingHelper(valName.value, x, n)
     def cross(n: IntInwardNode) (implicit valName: ValName) = crossIn(n)
     def cross(n: IntOutwardNode)(implicit valName: ValName) = crossOut(n)
   }
 
   implicit class IntResetDomainCrossing(private val x: HasResetDomainCrossing) extends AnyVal {
-    def crossIn (n: IntInwardNode) (implicit valName: ValName) = IntInwardResetCrossingHelper(valName.name, x, n)
-    def crossOut(n: IntOutwardNode)(implicit valName: ValName) = IntOutwardResetCrossingHelper(valName.name, x, n)
+    def crossIn (n: IntInwardNode) (implicit valName: ValName) = IntInwardResetCrossingHelper(valName.value, x, n)
+    def crossOut(n: IntOutwardNode)(implicit valName: ValName) = IntOutwardResetCrossingHelper(valName.value, x, n)
     def cross(n: IntInwardNode) (implicit valName: ValName) = crossIn(n)
     def cross(n: IntOutwardNode)(implicit valName: ValName) = crossOut(n)
   }

src/main/scala/jtag/JtagStateMachine.scala

@@ -15,7 +15,7 @@ object JtagState {
   object State {
     import scala.language.implicitConversions
 
-    implicit def toInt(x: State) = x.id
+    implicit def toInt(x: State): Int = x.id
     implicit def toBigInt(x: State):BigInt = x.id
 
     // TODO: this could be automatically generated with macros and stuff

src/main/scala/jtag/package.scala

@@ -11,5 +11,5 @@ package object jtag {
     *
     * This is limited to value types of Chain to limit application scope.
     */
-  implicit def instructionIntKeyToBigInt[V <: Chain](x: (Int, V)) = (BigInt(x._1), x._2)
+  implicit def instructionIntKeyToBigInt[V <: Chain](x: (Int, V)): (BigInt, V) = (BigInt(x._1), x._2)
 }

src/main/scala/prci/ClockGroup.scala

@@ -34,7 +34,7 @@ class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule
 
 object ClockGroup
 {
-  def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node
+  def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.value)).node
 }
 
 case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName)
@@ -63,7 +63,7 @@ class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends La
 
 object ClockGroupAggregator
 {
-  def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node
+  def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.value)).node
 }
 
 class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule

src/main/scala/prci/package.scala

@@ -2,6 +2,8 @@
 
 package freechips.rocketchip
 
+import scala.language.implicitConversions
+
 import org.chipsalliance.diplomacy.nodes._
 import freechips.rocketchip.diplomacy.{BufferParams}
 

src/main/scala/regmapper/RegField.scala

@@ -2,6 +2,8 @@
 
 package freechips.rocketchip.regmapper
 
+import scala.language.implicitConversions
+
 import chisel3._
 import chisel3.util.{DecoupledIO, ReadyValidIO}
 
@@ -18,7 +20,7 @@ object RegReadFn
   // all other combinational dependencies forbidden (e.g. ovalid <= ivalid)
   // effects must become visible on the cycle after ovalid && oready
   // data is only inspected when ovalid && oready
-  implicit def apply(x: (Bool, Bool) => (Bool, Bool, UInt)) =
+  implicit def apply(x: (Bool, Bool) => (Bool, Bool, UInt)): RegReadFn =
     new RegReadFn(false, x)
   implicit def apply(x: RegisterReadIO[UInt]): RegReadFn =
     RegReadFn((ivalid, oready) => {
@@ -29,7 +31,7 @@ object RegReadFn
   // (ready: Bool) => (valid: Bool, data: UInt)
   // valid must not combinationally depend on ready
   // effects must become visible on the cycle after valid && ready
-  implicit def apply(x: Bool => (Bool, UInt)) =
+  implicit def apply(x: Bool => (Bool, UInt)): RegReadFn =
     new RegReadFn(true, { case (_, oready) =>
       val (ovalid, data) = x(oready)
       (true.B, ovalid, data)
@@ -50,7 +52,7 @@ object RegWriteFn
   // all other combinational dependencies forbidden (e.g. ovalid <= ivalid)
   // effects must become visible on the cycle after ovalid && oready
   // data should only be used for an effect when ivalid && iready
-  implicit def apply(x: (Bool, Bool, UInt) => (Bool, Bool)) =
+  implicit def apply(x: (Bool, Bool, UInt) => (Bool, Bool)): RegWriteFn =
     new RegWriteFn(false, x)
   implicit def apply(x: RegisterWriteIO[UInt]): RegWriteFn =
     RegWriteFn((ivalid, oready, data) => {
@@ -62,7 +64,7 @@ object RegWriteFn
   // (valid: Bool, data: UInt) => (ready: Bool)
   // ready may combinationally depend on data (but not valid)
   // effects must become visible on the cycle after valid && ready
-  implicit def apply(x: (Bool, UInt) => Bool) =
+  implicit def apply(x: (Bool, UInt) => Bool): RegWriteFn =
     // combinational => data valid on oready
     new RegWriteFn(true, { case (_, oready, data) =>
       (true.B, x(oready, data))

src/main/scala/regmapper/RegMapper.scala

@@ -195,10 +195,10 @@ object RegMapper
       })
 
     // Include the per-register one-hot selected criteria
-    val rifireMux = mux(iindex, in.valid && front.ready &&  front.bits.read, frontSel, iRightReg, rifire)
-    val wifireMux = mux(iindex, in.valid && front.ready && !front.bits.read, frontSel, iRightReg, wifire)
-    val rofireMux = mux(oindex, back.valid && out.ready &&  back .bits.read, backSel,  oRightReg, rofire)
-    val wofireMux = mux(oindex, back.valid && out.ready && !back .bits.read, backSel,  oRightReg, wofire)
+    val rifireMux = mux(iindex, in.valid && front.ready &&  front.bits.read, frontSel, iRightReg.toIndexedSeq, rifire.toIndexedSeq)
+    val wifireMux = mux(iindex, in.valid && front.ready && !front.bits.read, frontSel, iRightReg.toIndexedSeq, wifire.toIndexedSeq)
+    val rofireMux = mux(oindex, back.valid && out.ready &&  back .bits.read, backSel,  oRightReg.toIndexedSeq, rofire.toIndexedSeq)
+    val wofireMux = mux(oindex, back.valid && out.ready && !back .bits.read, backSel,  oRightReg.toIndexedSeq, wofire.toIndexedSeq)
 
     val iready = Mux(front.bits.read, rifireMux, wifireMux)
     val oready = Mux(back .bits.read, rofireMux, wofireMux)
@@ -210,8 +210,8 @@ object RegMapper
     out.valid   := back.valid  && oready
 
     out.bits.read  := back.bits.read
-    out.bits.data  := Mux(MuxSeq(oindex, true.B, oRightReg),
-                          MuxSeq(oindex, 0.U, dataOut),
+    out.bits.data  := Mux(MuxSeq(oindex, true.B, oRightReg.toIndexedSeq),
+                          MuxSeq(oindex, 0.U, dataOut.toIndexedSeq),
                           0.U)
     out.bits.extra := back.bits.extra
 

src/main/scala/resources/AddressMapEntry.scala

@@ -17,5 +17,5 @@ case class AddressMapEntry(range: AddressRange, permissions: ResourcePermissions
 
   def toJSON = s"""{"base":[${range.base}],"size":[${range.size}],""" +
     s""""r":[$r],"w":[$w],"x":[$x],"c":[$c],"a":[$a],""" +
-    s""""names":[${names.map('"'+_+'"').mkString(",")}]}"""
+    s""""names":[${names.map(n => s""""$n"""").mkString(",")}]}"""
 }

src/main/scala/resources/DeviceTree.scala

@@ -137,6 +137,6 @@ object DTB
     require (proc.! == 0, "Failed to run dtc; is it in your path?")
     instream.close
     outstream.close
-    DTB(outstream.toByteArray)
+    DTB(outstream.toByteArray.toIndexedSeq)
   }
 }

src/main/scala/resources/Resources.scala

@@ -145,7 +145,7 @@ trait DeviceRegName
 {
   this: Device =>
   def describeName(devname: String, resources: ResourceBindings): String = {
-    val reg = resources.map.filterKeys(DiplomacyUtils.regFilter)
+    val reg = resources.map.view.filterKeys(DiplomacyUtils.regFilter).toMap
     if (reg.isEmpty) {
       devname
     } else {
@@ -195,7 +195,7 @@ class SimpleDevice(val devname: String, devcompat: Seq[String]) extends Device
     def optDef(x: String, seq: Seq[ResourceValue]) = if (seq.isEmpty) None else Some(x -> seq)
     val compat = optDef("compatible", devcompat.map(ResourceString(_))) // describe the list of compatiable devices
 
-    val reg = resources.map.filterKeys(DiplomacyUtils.regFilter)
+    val reg = resources.map.view.filterKeys(DiplomacyUtils.regFilter).toMap
     val (named, bulk) = reg.partition { case (k, v) => DiplomacyUtils.regName(k).isDefined }
     // We need to be sure that each named reg has exactly one AddressRange associated to it
     named.foreach {
@@ -252,7 +252,7 @@ class MemoryDevice extends Device with DeviceRegName
 {
   def describe(resources: ResourceBindings): Description = {
     Description(describeName("memory", resources), ListMap(
-      "reg"         -> resources.map.filterKeys(DiplomacyUtils.regFilter).flatMap(_._2).map(_.value).toList,
+      "reg"         -> resources.map.view.filterKeys(DiplomacyUtils.regFilter).toMap.flatMap(_._2).map(_.value).toList,
       "device_type" -> Seq(ResourceString("memory"))))
   }
 }
@@ -379,8 +379,8 @@ trait BindingScope
     */
   def getResourceBindingsMap: ResourceBindingsMap = {
     eval
-    ResourceBindingsMap(map = resourceBindings.reverse.groupBy(_._1.owner).mapValues(seq => ResourceBindings(
-        seq.groupBy(_._1.key).mapValues(_.map(z => Binding(z._2, z._3)).distinct).toMap)).toMap)
+    ResourceBindingsMap(map = resourceBindings.reverse.groupBy(_._1.owner).view.mapValues(seq => ResourceBindings(
+        seq.groupBy(_._1.key).view.mapValues(_.map(z => Binding(z._2, z._3)).distinct).toMap)).toMap)
   }
 
   /** Collect resource addresses from tree. */

src/main/scala/resources/SRAM.scala

@@ -5,8 +5,9 @@ package freechips.rocketchip.resources
 import chisel3._
 import chisel3.util.log2Ceil
 import org.chipsalliance.cde.config.Parameters
+import org.chipsalliance.diplomacy.lazymodule._
 import freechips.rocketchip.util.{DescribedSRAM, Code}
-import freechips.rocketchip.diplomacy.{AddressSet, LazyModule}
+import freechips.rocketchip.diplomacy.AddressSet
 
 abstract class DiplomaticSRAM(
     val address: AddressSet,

src/main/scala/rocket/BTB.scala

@@ -24,7 +24,7 @@ case class BTBParams(
   bhtParams: Option[BHTParams] = Some(BHTParams()),
   updatesOutOfOrder: Boolean = false)
 
-trait HasBtbParameters extends HasCoreParameters { this: InstanceId =>
+trait HasBtbParameters extends HasCoreParameters {
   val btbParams = tileParams.btb.getOrElse(BTBParams(nEntries = 0))
   val matchBits = btbParams.nMatchBits max log2Ceil(p(CacheBlockBytes) * tileParams.icache.get.nSets)
   val entries = btbParams.nEntries