Bump riscv-isa-sim from f45f726 to ec3c935#74
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Bumps [riscv-isa-sim](https://github.com/riscv/riscv-isa-sim) from `f45f726` to `ec3c935`. - [Release notes](https://github.com/riscv/riscv-isa-sim/releases) - [Commits](riscv-software-src/riscv-isa-sim@f45f726...ec3c935) --- updated-dependencies: - dependency-name: riscv-isa-sim dependency-type: direct:production ... Signed-off-by: dependabot[bot] <support@github.com>
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Bumps riscv-isa-sim from
f45f726toec3c935.Commits
ec3c935Merge pull request #1427 from YenHaoChen/pr-textra-sbytemaskc59e80eMerge pull request #1381 from rivosinc/smcntrpmf_featurec927773Add Smcntrpmf functionality6217853Add prv_changed / v_changed fields to state1c91fd5Regenerate encoding.h6337981triggers: fix textra.sbytemask60c08b1Merge pull request #1383 from rivosinc/sscrind_feature4d01719Merge pull request #1416 from YenHaoChen/pr-xenvcfg-cbiee7e1880legalize henvcfg.CBIE7f22022legalize senvcfg.CBIEDependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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