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Verilog: KNOWNBUG test for port connection that has typedef name #1411

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Merged
merged 1 commit into from
Nov 14, 2025
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Verilog: KNOWNBUG test for port connection that has typedef name #1411

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9 changes: 9 additions & 0 deletions regression/verilog/modules/port_connection1.desc
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KNOWNBUG
port_connection1.sv

^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
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@tautschnig tautschnig Nov 14, 2025

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I'd appreciate a note saying what is going wrong here.

--
This does not parse.
16 changes: 16 additions & 0 deletions regression/verilog/modules/port_connection1.sv
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module M(input [31:0] some_name);

initial assert (some_name == 123);

endmodule

module main;

// typedef with the same name as a port
typedef bit [31:0] some_name;

// This fails to parse with Icarus Verilog,
// but works with VCS, Questa, Xcelium, Riviera
M my_instance(.some_name(123));

endmodule
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