[Arista] Jericho4L cModel: WIP Vendor mappings for bringup#951

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jstnzl wants to merge 16 commits intofacebook:mainfrom

jstnzl:j4sim_map_upstream

Commits on Feb 20, 2026

Add dummy Trace.csv for j4sim
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Making some platform changes to get vendor mappings later
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Generated vendor mappings
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Platform mapping changes following PR1496, needs creation still
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Update trace csv and vendor mappings
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More fixes and add platform mapping
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Add ASIC_TYPE_JERICHO4 to AsicType enum
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Add Jericho4Asic.h and make J4Sim stuff use it instead of Q4DAsic.h
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Update Jericho4Asic to inherit from Jericho3Asic, and set max port speed 200G
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Changes to get generate.py working, and exclude all except pm config
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Fix J4 not inheriting from J3
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Address comments, and make changes to get build working for J4Sim/Jericho4
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Taking more changes from Satish's diff, still failing -- j4 cmodel is actually j4l?
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Changes to all the J4Sim to work with J4L instead (4 cores). Used config-j4l.bcm in j4 cmodel tarball to figure out values to use and stuff
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Add JSON to J4SimPlatformMapping.cpp so it gets loaded when we run cModel testing, also added j4sim mode to the hw_test_config
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Commits on Feb 24, 2026

Get past existing failures, hitting some brcm_sai_dnx_crps_database_create failure now
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