update readmes

README.md

@@ -1,62 +1,71 @@
 # Questions, Codes & Their Solutions
 
-## Try these questions on your own before you head to the solutions.
+## Try these questions on your own before you head to the solutions. 
 
-Q1: Implement a 4-bit register using D flip-flops.
+Q1: Registers
 
-[Solution Code: ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q1/register.v)  
-[Testbench Code: ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q1/register_tb.v)
+[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q1/README.md)
+[Solution Code ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q1/register.v)  
+[Testbench Code ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q1/register_tb.v)
 
 
-Q2: Implement an 8-bit register using behavioral modeling with a single read and write port such that both read and write operations can occur simultaneously, but when they do read is given more priority.
+Q2: Registers
 
-[Solution Code: ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q2/registeroperations.v)  
-[Testbench Code: ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q2/registeroperations_tb.v)
+[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q2/README.md)
+[Solution Code ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q2/registeroperations.v)  
+[Testbench Code ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q2/registeroperations_tb.v)
 
 
-Q3: Implement an 8-bit SISO shift register using behavioral modeling.
+Q3: Shift Registers
 
-[Solution Code: ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q3/shiftregister_SISO.v)  
-[Testbench Code: ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q3/shiftregister_SISO_tb.v)
+[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q3/README.md)
+[Solution Code ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q3/shiftregister_SISO.v)  
+[Testbench Code ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q3/shiftregister_SISO_tb.v)
 
 
-Q4: Implement an 8-bit SIPO shift register using behavioral modeling.
+Q4: Shift Registers
 
+[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q4/README.md)
 [Solution Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q4/shiftregister_SIPO.v)   
 [Testbench Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q4/shiftregister_SIPO_tb.v)
 
 
-Q5: Implement an 8-bit PISO shift register using behavioral modeling.
+Q5: Shift Registers
 
+[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q5/README.md)
 [Solution Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q5/shiftregister_PISO.v)  
 [Testbench Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q5/shiftregister_PISO_tb.v)
 
 
-Q6: Implement an 8-bit PIPO shift register using behavioral modeling.
+Q6: Shift Registers
 
+[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q6/README.md)
 [Solution Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q6/shiftregister_PIPO.v)   
 [Testbench Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q6/shiftregister_PIPO_tb.v)
 
-Q7: Implement an 8-bit register with 1 read port and 2 write ports. Either read or write is permitted at a time and when you perform write, you are to write through the two write ports alternately.
+Q7: Registers
 
+[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q7/README.md)
 [Solution Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q7/regnew.v)  
 [Testbench Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q7/regnew_tb.v)
 
 
-Q8: Implement an 8-bit register file with 8 registers such that only a read or write can oc
-cur at a time.
+Q8: Register File
 
+[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q8/README.md)
 [Solution Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q8/regfile2.v)  
 [Testbench Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q8/regfile2_tb.v)
 
 
-Q9: Implement a 64-bit register file with 32 register with 4 read ports and 2 write ports. Multiple operations can occur at a time, but the lower port is given more priority in such cases. Read > Write .
+Q9: Register File
 
+[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q9/README.md)
 [Solution Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q9/regfile3.v)  
 [Testbench Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q9/regfile3_tb.v)
 
-Q10: Implement a 4-bit universal shift register.
+Q10: Universal Shift Register
 
+[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q10/README.md)
 [Solution Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q10/universal_shift_register.v)  
 [Testbench Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q10/universal_shift_register_tb.v)
 

codes/Q1/README.md

@@ -0,0 +1 @@
+Implement a 4-bit register using D flip-flops.

codes/Q10/README.md

@@ -0,0 +1 @@
+Implement a 4-bit universal shift register.

codes/Q2/README.md

@@ -0,0 +1 @@
+Implement an 8-bit register using behavioral modeling with a single read and write port such that both read and write operations can occur simultaneously, but when they do read is given more priority.

codes/Q3/README.md

@@ -0,0 +1 @@
+Implement an 8-bit SISO shift register using behavioral modeling.

codes/Q4/README.md

@@ -0,0 +1 @@
+Implement an 8-bit SIPO shift register using behavioral modeling.

codes/Q5/README.md

@@ -0,0 +1 @@
+Implement an 8-bit PISO shift register using behavioral modeling.

codes/Q6/README.md

@@ -0,0 +1 @@
+Implement an 8-bit PIPO shift register using behavioral modeling.

codes/Q7/README.md

@@ -0,0 +1 @@
+Implement an 8-bit register with 1 read port and 2 write ports. Either read or write is permitted at a time and when you perform write, you are to write through the two write ports alternately.

codes/Q8/README.md

@@ -0,0 +1 @@
+Implement an 8-bit register file with 8 registers such that only a read or write can occur at a time.

codes/Q9/README.md

@@ -0,0 +1 @@
+Implement a 64-bit register file with 32 register with 4 read ports and 2 write ports. Multiple operations can occur at a time, but the lower port is given more priority in such cases. Read > Write .