DFCIR: CombinifyPass

src/model/dfcir/include/dfcir/DFCIROperations.td

@@ -22,7 +22,7 @@ include "mlir/IR/OpBase.td"
 class DFCIR_Op<string name, list<Trait> traits = []> : Op<DFCIR_Dialect, name, traits>;
 
 def KernelOp : DFCIR_Op<"kernel", 
-    [NoRegionArguments, NoTerminator, SingleBlock]> {
+    [IsolatedFromAbove, NoRegionArguments, NoTerminator, SingleBlock]> {
   let summary = "Defines a dataflow kernel.";
 
   let arguments = (ins

src/model/dfcir/include/dfcir/passes/DFCIRPasses.h

@@ -72,7 +72,9 @@ namespace mlir::dfcir {
 using std::unique_ptr;
 using mlir::Pass;
 
-unique_ptr<Pass> createDFCIRCombPipelinePassPass(uint64_t stages);
+unique_ptr<Pass> createDFCIRCombinifyPass();
+
+unique_ptr<Pass> createDFCIRCombPipelinePass(uint64_t stages);
 
 unique_ptr<Pass> createDFCIRToFIRRTLPass();
 

src/model/dfcir/include/dfcir/passes/DFCIRPasses.td

@@ -31,6 +31,12 @@ def DFCIRCombPipelinePass: Pass<"dfcir-comb-pipeline-pass", "mlir::ModuleOp"> {
   ];
 }
 
+def DFCIRCombinifyPass: Pass<"dfcir-combinify-pass", "mlir::dfcir::KernelOp"> {
+  let summary = "Explicitly sets latency '0' for every '?' latency in the kernel.";
+
+  let constructor = "mlir::dfcir::createDFCIRCombinifyPass()";
+}
+
 class DFCIRSchedulerPass<string name, string op>: Pass<name, op> {
 
   let options = [

src/model/dfcir/lib/dfcir/passes/CMakeLists.txt

@@ -6,6 +6,7 @@ add_compile_options(-Wno-overloaded-virtual)
 
 add_mlir_library(UtopiaDFCIRPasses
   ${CMAKE_CURRENT_SOURCE_DIR}/DFCIRASAPSchedulerPass.cpp
+  ${CMAKE_CURRENT_SOURCE_DIR}/DFCIRCombinifyPass.cpp
   ${CMAKE_CURRENT_SOURCE_DIR}/DFCIRCombPipelinePass.cpp
   ${CMAKE_CURRENT_SOURCE_DIR}/DFCIRLinearSchedulerPass.cpp
   ${CMAKE_CURRENT_SOURCE_DIR}/DFCIRLPUtils.cpp

src/model/dfcir/lib/dfcir/passes/DFCIRCombPipelinePass.cpp

@@ -54,7 +54,7 @@ class DFCIRCombPipelinePass
   }
 };
 
-std::unique_ptr<mlir::Pass> createDFCIRCombPipelinePassPass(uint64_t stages) {
+std::unique_ptr<mlir::Pass> createDFCIRCombPipelinePass(uint64_t stages) {
   DFCIRCombPipelinePassOptions options;
   options.stages = stages;
   return std::make_unique<DFCIRCombPipelinePass>(options);

src/model/dfcir/lib/dfcir/passes/DFCIRCombinifyPass.cpp

@@ -0,0 +1,41 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the Utopia HLS Project, under the Apache License v2.0
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2025 ISP RAS (http://www.ispras.ru)
+//
+//===----------------------------------------------------------------------===//
+
+#include "dfcir/passes/DFCIRPasses.h"
+#include "dfcir/passes/DFCIRPassesUtils.h"
+#include "circt/Support/LLVM.h"
+#include "mlir/IR/Dialect.h"
+
+namespace mlir::dfcir {
+#define GEN_PASS_DECL_DFCIRCOMBINIFYPASS
+#define GEN_PASS_DEF_DFCIRCOMBINIFYPASS
+
+#include "dfcir/passes/DFCIRPasses.h.inc"
+
+class DFCIRCombinifyPass
+    : public impl::DFCIRCombinifyPassBase<DFCIRCombinifyPass> {
+
+public:
+  explicit DFCIRCombinifyPass()
+      : impl::DFCIRCombinifyPassBase<DFCIRCombinifyPass>() {}
+
+  void runOnOperation() override {
+    KernelOp kernel = mlir::cast<KernelOp>(getOperation());
+    Block &block = kernel.getBody().front();
+
+    for (Scheduled sched: block.getOps<Scheduled>()) {
+      sched.setLatency(0);
+    }
+  }
+};
+
+std::unique_ptr<mlir::Pass> createDFCIRCombinifyPass() {
+  return std::make_unique<DFCIRCombinifyPass>();
+}
+
+} // namespace mlir::dfcir

src/model/dfcxx/lib/dfcxx/dfcir_processor.cpp

@@ -74,7 +74,12 @@ bool DFCIRProcessor::convertAndPrint(mlir::ModuleOp module,
       pm.addPass(mlir::dfcir::createDFCIRASAPSchedulerPass(&config));
       break;
     case CombPipelining:
-      pm.addPass(mlir::dfcir::createDFCIRCombPipelinePassPass(options.stages));
+      if (!options.stages) {
+        mlir::OpPassManager &nestedDfcir = pm.nest<mlir::dfcir::KernelOp>();
+        nestedDfcir.addPass(mlir::dfcir::createDFCIRCombinifyPass());
+      } else {
+        pm.addPass(mlir::dfcir::createDFCIRCombPipelinePass(options.stages));
+      }
       break;
   }