EECS 151/251A FPGA Project Skeleton for Fall 2021

Check out the Project Overview.

Checkpoint 1: 3-stage RISC-V (rv32ui) Processor Block Design Diagram

Checkpoint 2: Fully functional 3-stage RISC-V (rv32ui) Processor

Checkpoint 3: Integration of IO Circuits and NCO/DAC

Checkpoint 4: Design of an PDM mic circuit and BPM detector

Checkpoint 5: Processor Optimization (100MHz)

• Specs
  • Checkpoint 1 and 2 spec

Resources:

• RISC-V ISA Manual (Sections 2.2 - 2.6)
• FPGA Labs Fall 2021