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This is to display a bug in real true16 mode that we do not have
an allocatable 16-bit VGPR class and these instructions do not
have VOP3 forms for allocatable VGPR_16 to be used. To use these
instructions 'VGPR_16_Lo128' must be allocable.

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rampitec commented Dec 22, 2025

@rampitec rampitec marked this pull request as ready for review December 22, 2025 20:34
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llvmbot commented Dec 22, 2025

@llvm/pr-subscribers-backend-amdgpu

Author: Stanislav Mekhanoshin (rampitec)

Changes

This is to display a bug in real true16 mode that we do not have
an allocatable 16-bit VGPR class and these instructions do not
have VOP3 forms for allocatable VGPR_16 to be used. To use these
instructions 'VGPR_16_Lo128' must be allocable.


Full diff: https://github.com/llvm/llvm-project/pull/173307.diff

1 Files Affected:

  • (added) llvm/test/CodeGen/AMDGPU/fmamk_fmaak-t16.mir (+31)
diff --git a/llvm/test/CodeGen/AMDGPU/fmamk_fmaak-t16.mir b/llvm/test/CodeGen/AMDGPU/fmamk_fmaak-t16.mir
new file mode 100644
index 0000000000000..75aa62b63e832
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/fmamk_fmaak-t16.mir
@@ -0,0 +1,31 @@
+# RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=machineverifier -filetype=null %s 2>&1 | FileCheck %s -check-prefix=GFX11
+# RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -start-before=greedy,0 -stop-after=virtregrewriter,2 -o - %s 2>&1 | FileCheck %s -check-prefix=GFX11
+
+# FIXME: There is no allocatable 16-bit VGPR class and these instructions
+#        do not have VOP3 forms for allocatable VGPR_16 to be used.
+
+# GFX11: Cannot use non-allocatable class 'VGPR_16_Lo128' for virtual register
+
+---
+name:            v_fmamk_f16
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    %0:vgpr_32_lo128 = COPY $vgpr0
+    %1:vgpr_32_lo128 = COPY $vgpr1
+    %2:vgpr_16_lo128 = nofpexcept V_FMAMK_F16_t16 %0.sub0, 1, %1.sub1, implicit $exec, implicit $mode
+    S_ENDPGM 0, implicit %2
+...
+
+---
+name:            v_fmaak_f16
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    %0:vgpr_32_lo128 = COPY $vgpr0
+    %1:vgpr_32_lo128 = COPY $vgpr1
+    %2:vgpr_16_lo128 = nofpexcept V_FMAAK_F16_t16 %0.sub0, %1.sub1, 1, implicit $exec, implicit $mode
+    S_ENDPGM 0, implicit %2
+...

This is to display a bug in real true16 mode that we do not have
an allocatable 16-bit VGPR class and these instructions do not
have VOP3 forms for allocatable VGPR_16 to be used. To use these
instructions 'VGPR_16_Lo128' must be allocable.
Comment on lines +1 to +2
# RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=machineverifier -filetype=null %s 2>&1 | FileCheck %s -check-prefix=GFX11
# RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -start-before=greedy,0 -stop-after=virtregrewriter,2 -o - %s 2>&1 | FileCheck %s -check-prefix=GFX11
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Suggested change
# RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=machineverifier -filetype=null %s 2>&1 | FileCheck %s -check-prefix=GFX11
# RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -start-before=greedy,0 -stop-after=virtregrewriter,2 -o - %s 2>&1 | FileCheck %s -check-prefix=GFX11
# RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=none -filetype=null %s 2>&1 | FileCheck -check-prefix=GFX11 %s
# RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -start-before=greedy,0 -stop-after=virtregrewriter,2 -o - %s 2>&1 | FileCheck -check-prefix=GFX11 %s

Comment on lines +1 to +2
# RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=machineverifier -filetype=null %s 2>&1 | FileCheck %s -check-prefix=GFX11
# RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -start-before=greedy,0 -stop-after=virtregrewriter,2 -o - %s 2>&1 | FileCheck %s -check-prefix=GFX11
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I'm not sure what the point of the second run line is, the error seems to come from the MIR parser (instead of the machine verifier, for some reason)?

Test also belongs in test/MachineVerifier or CodeGen/MIR

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4 participants