-
Notifications
You must be signed in to change notification settings - Fork 15.6k
[AMDGPU] Add test for v_fmamk_f16/v_fmaak_f16 in real-true16. NFC #173307
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
base: main
Are you sure you want to change the base?
Conversation
|
@llvm/pr-subscribers-backend-amdgpu Author: Stanislav Mekhanoshin (rampitec) ChangesThis is to display a bug in real true16 mode that we do not have Full diff: https://github.com/llvm/llvm-project/pull/173307.diff 1 Files Affected:
diff --git a/llvm/test/CodeGen/AMDGPU/fmamk_fmaak-t16.mir b/llvm/test/CodeGen/AMDGPU/fmamk_fmaak-t16.mir
new file mode 100644
index 0000000000000..75aa62b63e832
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/fmamk_fmaak-t16.mir
@@ -0,0 +1,31 @@
+# RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=machineverifier -filetype=null %s 2>&1 | FileCheck %s -check-prefix=GFX11
+# RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -start-before=greedy,0 -stop-after=virtregrewriter,2 -o - %s 2>&1 | FileCheck %s -check-prefix=GFX11
+
+# FIXME: There is no allocatable 16-bit VGPR class and these instructions
+# do not have VOP3 forms for allocatable VGPR_16 to be used.
+
+# GFX11: Cannot use non-allocatable class 'VGPR_16_Lo128' for virtual register
+
+---
+name: v_fmamk_f16
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ %0:vgpr_32_lo128 = COPY $vgpr0
+ %1:vgpr_32_lo128 = COPY $vgpr1
+ %2:vgpr_16_lo128 = nofpexcept V_FMAMK_F16_t16 %0.sub0, 1, %1.sub1, implicit $exec, implicit $mode
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: v_fmaak_f16
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ %0:vgpr_32_lo128 = COPY $vgpr0
+ %1:vgpr_32_lo128 = COPY $vgpr1
+ %2:vgpr_16_lo128 = nofpexcept V_FMAAK_F16_t16 %0.sub0, %1.sub1, 1, implicit $exec, implicit $mode
+ S_ENDPGM 0, implicit %2
+...
|
This is to display a bug in real true16 mode that we do not have an allocatable 16-bit VGPR class and these instructions do not have VOP3 forms for allocatable VGPR_16 to be used. To use these instructions 'VGPR_16_Lo128' must be allocable.
13a5812 to
9ca1757
Compare
| # RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=machineverifier -filetype=null %s 2>&1 | FileCheck %s -check-prefix=GFX11 | ||
| # RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -start-before=greedy,0 -stop-after=virtregrewriter,2 -o - %s 2>&1 | FileCheck %s -check-prefix=GFX11 |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
| # RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=machineverifier -filetype=null %s 2>&1 | FileCheck %s -check-prefix=GFX11 | |
| # RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -start-before=greedy,0 -stop-after=virtregrewriter,2 -o - %s 2>&1 | FileCheck %s -check-prefix=GFX11 | |
| # RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=none -filetype=null %s 2>&1 | FileCheck -check-prefix=GFX11 %s | |
| # RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -start-before=greedy,0 -stop-after=virtregrewriter,2 -o - %s 2>&1 | FileCheck -check-prefix=GFX11 %s |
| # RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=machineverifier -filetype=null %s 2>&1 | FileCheck %s -check-prefix=GFX11 | ||
| # RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -start-before=greedy,0 -stop-after=virtregrewriter,2 -o - %s 2>&1 | FileCheck %s -check-prefix=GFX11 |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
I'm not sure what the point of the second run line is, the error seems to come from the MIR parser (instead of the machine verifier, for some reason)?
Test also belongs in test/MachineVerifier or CodeGen/MIR
This is to display a bug in real true16 mode that we do not have
an allocatable 16-bit VGPR class and these instructions do not
have VOP3 forms for allocatable VGPR_16 to be used. To use these
instructions 'VGPR_16_Lo128' must be allocable.