[AMDGPU] Make VGPR_16_Lo128 allocatable

[rampitec]

Allows allocation of V_FMAMK_F16/V_FMAAK_F16 registers in
real true16 mode.

[rampitec]

• [AMDGPU] Allow 16-bit imm folding in real true16 #173318
• [AMDGPU] Create V_FMAAK_F16/V_FMAMK_F16 in true16 with imm folding #173317
• [AMDGPU] Make VGPR_16_Lo128 allocatable #173309 👈
• [AMDGPU] Add test for v_fmamk_f16/v_fmaak_f16 in real-true16. NFC #173307
• main

This stack of pull requests is managed by sgh.

[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

Author: Stanislav Mekhanoshin (rampitec)

Changes

Allows allocation of V_FMAMK_F16/V_FMAAK_F16 registers in
real true16 mode.

---

Full diff: https://github.com/llvm/llvm-project/pull/173309.diff

2 Files Affected:

• (modified) llvm/lib/Target/AMDGPU/SIRegisterInfo.td (+1-1)
• (modified) llvm/test/CodeGen/AMDGPU/fmamk_fmaak-t16.mir (+12-7)

diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index 272d4b5609dfb..8d9fd3662b760 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -614,9 +614,9 @@ def VGPR_16 : SIRegisterClass<"AMDGPU",  Reg16Types.types, 16,
 def VGPR_16_Lo128 : SIRegisterClass<"AMDGPU",  Reg16Types.types, 16,
                             (add (interleave (sequence "VGPR%u_LO16", 0, 127),
                                              (sequence "VGPR%u_HI16", 0, 127)))> {
+  let AllocationPriority = !add(2, !mul(BaseClassPriority, BaseClassScaleFactor));
   let Size = 16;
   let GeneratePressureSet = 0;
-  let isAllocatable = 0;
 
   // This is the base class for VGPR{0..127}_{LO16,HI16}.
   let BaseClassOrder = 16;
diff --git a/llvm/test/CodeGen/AMDGPU/fmamk_fmaak-t16.mir b/llvm/test/CodeGen/AMDGPU/fmamk_fmaak-t16.mir
index b3d9a56ef300e..3eec7f95a976f 100644
--- a/llvm/test/CodeGen/AMDGPU/fmamk_fmaak-t16.mir
+++ b/llvm/test/CodeGen/AMDGPU/fmamk_fmaak-t16.mir
@@ -1,10 +1,5 @@
-# RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=machineverifier -filetype=null %s 2>&1 | FileCheck %s -check-prefix=GFX11
-# RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -start-before=greedy,0 -stop-after=virtregrewriter,2 -o - %s 2>&1 | FileCheck %s -check-prefix=GFX11
-
-# FIXME: There is no allocatable 16-bit VGPR class and these instructions
-#        do not have VOP3 forms for allocatable VGPR_16 to be used.
-
-# GFX11: Cannot use non-allocatable class 'VGPR_16_Lo128' for virtual register
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -start-before=greedy,0 -stop-after=virtregrewriter,2 -o - %s | FileCheck %s -check-prefix=GFX11
 
 ---
 name:            v_fmamk_f16
@@ -12,6 +7,11 @@ tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
+    ; GFX11-LABEL: name: v_fmamk_f16
+    ; GFX11: liveins: $vgpr0, $vgpr1
+    ; GFX11-NEXT: {{  $}}
+    ; GFX11-NEXT: renamable $vgpr0_lo16 = nofpexcept V_FMAMK_F16_t16 killed $vgpr0_lo16, 1, killed $vgpr1_hi16, implicit $exec, implicit $mode
+    ; GFX11-NEXT: S_ENDPGM 0, implicit killed renamable $vgpr0_lo16
     %0:vgpr_32_lo128 = COPY $vgpr0
     %1:vgpr_32_lo128 = COPY $vgpr1
     %2:vgpr_16_lo128 = nofpexcept V_FMAMK_F16_t16 %0.lo16, 1, %1.hi16, implicit $exec, implicit $mode
@@ -24,6 +24,11 @@ tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
+    ; GFX11-LABEL: name: v_fmaak_f16
+    ; GFX11: liveins: $vgpr0, $vgpr1
+    ; GFX11-NEXT: {{  $}}
+    ; GFX11-NEXT: renamable $vgpr0_lo16 = nofpexcept V_FMAAK_F16_t16 killed $vgpr0_lo16, killed $vgpr1_hi16, 1, implicit $exec, implicit $mode
+    ; GFX11-NEXT: S_ENDPGM 0, implicit killed renamable $vgpr0_lo16
     %0:vgpr_32_lo128 = COPY $vgpr0
     %1:vgpr_32_lo128 = COPY $vgpr1
     %2:vgpr_16_lo128 = nofpexcept V_FMAAK_F16_t16 %0.lo16, %1.hi16, 1, implicit $exec, implicit $mode