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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIRegisterInfo.td
Original file line number Diff line number Diff line change
Expand Up @@ -614,9 +614,9 @@ def VGPR_16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16,
def VGPR_16_Lo128 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16,
(add (interleave (sequence "VGPR%u_LO16", 0, 127),
(sequence "VGPR%u_HI16", 0, 127)))> {
let AllocationPriority = !add(2, !mul(BaseClassPriority, BaseClassScaleFactor));
let Size = 16;
let GeneratePressureSet = 0;
let isAllocatable = 0;

// This is the base class for VGPR{0..127}_{LO16,HI16}.
let BaseClassOrder = 16;
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19 changes: 12 additions & 7 deletions llvm/test/CodeGen/AMDGPU/fmamk_fmaak-t16.mir
Original file line number Diff line number Diff line change
@@ -1,17 +1,17 @@
# RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=machineverifier -filetype=null %s 2>&1 | FileCheck %s -check-prefix=GFX11
# RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -start-before=greedy,0 -stop-after=virtregrewriter,2 -o - %s 2>&1 | FileCheck %s -check-prefix=GFX11

# FIXME: There is no allocatable 16-bit VGPR class and these instructions
# do not have VOP3 forms for allocatable VGPR_16 to be used.

# GFX11: Cannot use non-allocatable class 'VGPR_16_Lo128' for virtual register
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -start-before=greedy,0 -stop-after=virtregrewriter,2 -o - %s | FileCheck %s -check-prefix=GFX11

---
name: v_fmamk_f16
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; GFX11-LABEL: name: v_fmamk_f16
; GFX11: liveins: $vgpr0, $vgpr1
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: renamable $vgpr0_lo16 = nofpexcept V_FMAMK_F16_t16 killed $vgpr0_lo16, 1, killed $vgpr1_hi16, implicit $exec, implicit $mode
; GFX11-NEXT: S_ENDPGM 0, implicit killed renamable $vgpr0_lo16
%0:vgpr_32_lo128 = COPY $vgpr0
%1:vgpr_32_lo128 = COPY $vgpr1
%2:vgpr_16_lo128 = nofpexcept V_FMAMK_F16_t16 %0.lo16, 1, %1.hi16, implicit $exec, implicit $mode
Expand All @@ -24,6 +24,11 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; GFX11-LABEL: name: v_fmaak_f16
; GFX11: liveins: $vgpr0, $vgpr1
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: renamable $vgpr0_lo16 = nofpexcept V_FMAAK_F16_t16 killed $vgpr0_lo16, killed $vgpr1_hi16, 1, implicit $exec, implicit $mode
; GFX11-NEXT: S_ENDPGM 0, implicit killed renamable $vgpr0_lo16
%0:vgpr_32_lo128 = COPY $vgpr0
%1:vgpr_32_lo128 = COPY $vgpr1
%2:vgpr_16_lo128 = nofpexcept V_FMAAK_F16_t16 %0.lo16, %1.hi16, 1, implicit $exec, implicit $mode
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