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@Ta-ras Ta-ras commented Nov 28, 2025

  • Add simulator support for Infineon PSOC Edge E81–E84 silicon, enforce a minimum write size of 16 bytes
  • Add the "max-align-16" feature to the simulator and CI/CD test workflows

@Ta-ras Ta-ras force-pushed the pr/infineon-max-align-16 branch from 09072f9 to 404d70b Compare November 28, 2025 08:37
Signed-off-by: Taras <Taras.B@infineon.com>
@Ta-ras Ta-ras force-pushed the pr/infineon-max-align-16 branch from 404d70b to 3a2546c Compare November 28, 2025 08:45
@Ta-ras Ta-ras marked this pull request as ready for review November 28, 2025 09:31
@Ta-ras Ta-ras requested a review from d3zd3z as a code owner November 28, 2025 09:31
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I'm ok with this change, but I do think we should hold off merging until 2.3.0 is released.

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2 participants