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[obi_cut]: Fixed sbr_port_rsp_o.gnt stuck at 1 #31

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[obi_cut]: Fixed sbr_port_rsp_o.gnt stuck at 1 #31

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12 changes: 10 additions & 2 deletions src/obi_cut.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -32,20 +32,28 @@
input obi_rsp_t mgr_port_rsp_i
);

// PATCH: Internal ready signal to fix OBI protocol violation
// BUG FIX: spill_register can assert ready_o even when valid_i=0,
// violating OBI protocol which requires gnt=0 when req=0
logic internal_ready;

spill_register #(
.T ( obi_a_chan_t ),
.Bypass ( BypassReq )
) i_reg_a (
.clk_i,
.rst_ni,
.valid_i ( sbr_port_req_i.req ),
.ready_o ( sbr_port_rsp_o.gnt ),
.ready_o ( internal_ready ), // Use internal signal
.data_i ( sbr_port_req_i.a ),
.valid_o ( mgr_port_req_o.req ),
.ready_i ( mgr_port_rsp_i.gnt ),
.data_o ( mgr_port_req_o.a )
);

// PATCH: Ensure gnt=0 when req=0 to comply with OBI protocol
assign sbr_port_rsp_o.gnt = internal_ready & sbr_port_req_i.req;

logic ready_o;
logic ready_i;

Expand All @@ -70,4 +78,4 @@
.data_o ( sbr_port_rsp_o.r )
);

endmodule
endmodule

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[verible-verilog-lint] src/obi_cut.sv#L81 

File must end with a newline. [Style: posix-file-endings] [posix-eof]
Raw output 
message:"File must end with a newline. [Style: posix-file-endings] [posix-eof]" location:{path:"./src/obi_cut.sv" range:{start:{line:81 column:10}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:81 column:10} end:{line:82}} text:"endmodule\n"}