Pull Requests Since v2.59.0
Unlabeled
- #1275 - removing base/vhdl-libs
- #1276 - More sim testbed clean up
- #1274 - VHDL Simulation Updates
- #1205 - AxiSpiMaster - Fix bug in shadow RAM for multi-chip configurations
- #1279 - Sensitivity list fix in AxiStreamDepacketizer2
- #1277 - corner case fix for AxiStreamPkg.vhd
- #1272 - HTPS bug fix for 1024b AXIS stream
Pull Request Details
AxiSpiMaster - Fix bug in shadow RAM for multi-chip configurations
| Author: | Benjamin Reese bengineerd@users.noreply.github.com |
| Date: | Mon May 12 12:35:27 2025 -0700 |
| Pull: | #1205 (31 additions, 17 deletions, 1 files changed) |
| Branch: | slaclab/axi-spi-master |
Notes:
Description
The
SHADOW_EN_Gfeature that reads from a shadow RAM was broken for cases whenSPI_NUM_CHIPS_G > 1.
It would use the same shadow RAM of all chips. The RAM size has been increased so that there is a separate address space in the RAM for each chip.
HTPS bug fix for 1024b AXIS stream
| Author: | Larry Ruckman ruckman@slac.stanford.edu |
| Date: | Thu May 1 13:32:08 2025 -0700 |
| Pull: | #1272 (2 additions, 2 deletions, 1 files changed) |
| Branch: | slaclab/htps-update |
Notes:
Description
- Required due to recent increase of AXI stream width from 512b to 1024b
- Refer to #1247
VHDL Simulation Updates
| Author: | Larry Ruckman ruckman@slac.stanford.edu |
| Date: | Tue May 6 12:00:32 2025 -0700 |
| Pull: | #1274 (179 additions, 47 deletions, 37 files changed) |
| Branch: | slaclab/sim-testbed-clean-up |
Notes:
Description
- 'Simulation Passed' should assert 'note' (not 'failure') when the VHDL pass
- adding test_HammingEccTb.py as an example cocoTB + self-checking VHDL sim
- update CI to run the cocoTB pytest in parallel (instead of tests serially) to reduce CI time
- update CI to run the VSG in parallel (instead of tests serially) to reduce CI time
removing base/vhdl-libs
| Author: | Larry Ruckman ruckman@slac.stanford.edu |
| Date: | Tue May 6 12:00:18 2025 -0700 |
| Pull: | #1275 (0 additions, 115752 deletions, 87 files changed) |
| Branch: | slaclab/remove-copy-of-ieee-lib |
Notes:
Description
- Remove "copy" of IEEE VHDL that are not required
- Toolchain copy of these library files should be used instead
More sim testbed clean up
| Author: | Larry Ruckman ruckman@slac.stanford.edu |
| Date: | Mon May 12 12:12:35 2025 -0700 |
| Pull: | #1276 (1382 additions, 520 deletions, 90 files changed) |
| Branch: | slaclab/more-sim-testbed-clean-up |
Notes:
Description
- BUG FIX for axiStreamGetUserField & axiStreamSetUserField
- DSP code reorg
- adding test_AxiRamTb.py
- adding test_AxiRingBufferTb.py
- adding test_AxiStreamBytePackerTb.py
- adding test_AxiStreamPipelineTb.py
- adding test_AxiStreamPkgTb.py
- adding test_AxiStreamResizeTb.py
- adding test_AxiStreamDmaReadTb.py
- adding test_SlvDelayRamTb.py
- adding test_FwftCntTb.py
- adding test_DspComparatorTb.py
- adding test_SsiResizeFifoEofeTb.py
- adding test_SsiPrbsTb.py
- adding test_SrpV3AxiTb.py
corner case fix for AxiStreamPkg.vhd
| Author: | Larry Ruckman ruckman@slac.stanford.edu |
| Date: | Fri May 16 09:51:08 2025 -0700 |
| Pull: | #1277 (2 additions, 2 deletions, 1 files changed) |
| Branch: | slaclab/AxiStreamPkg-pathc |
Notes:
Description
- Prevent
for loopbeing beyond the range of thetUser- Reminder that the loop is required (instead of setting the field directly) due to capability with Cadence Genus support
Sensitivity list fix in AxiStreamDepacketizer2
| Author: | Larry Ruckman ruckman@slac.stanford.edu |
| Date: | Fri May 16 10:26:36 2025 -0700 |
| Pull: | #1279 (6 additions, 3 deletions, 2 files changed) |
| Branch: | slaclab/sensitivity-list-fix |
Notes:
Description
There is a bug in the emacs vhdl-mode sensitivity list generator that doesn't catch that
crcOutis used in the process.
This is probably because its usage is buried in a procedure.
The signal has been manually added to the sensitivity list.