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Patch Release v2.59.1

16 May 17:40
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v2.59.1
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Patch Release v2.59.1 Latest
Latest

Pull Requests Since v2.59.0

Unlabeled

  1. #1275 - removing base/vhdl-libs
  2. #1276 - More sim testbed clean up
  3. #1274 - VHDL Simulation Updates
  4. #1205 - AxiSpiMaster - Fix bug in shadow RAM for multi-chip configurations
  5. #1279 - Sensitivity list fix in AxiStreamDepacketizer2
  6. #1277 - corner case fix for AxiStreamPkg.vhd
  7. #1272 - HTPS bug fix for 1024b AXIS stream

Pull Request Details

AxiSpiMaster - Fix bug in shadow RAM for multi-chip configurations
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Mon May 12 12:35:27 2025 -0700
Pull: #1205 (31 additions, 17 deletions, 1 files changed)
Branch: slaclab/axi-spi-master

Notes:

Description

The SHADOW_EN_G feature that reads from a shadow RAM was broken for cases when SPI_NUM_CHIPS_G > 1.
It would use the same shadow RAM of all chips. The RAM size has been increased so that there is a separate address space in the RAM for each chip.

HTPS bug fix for 1024b AXIS stream
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu May 1 13:32:08 2025 -0700
Pull: #1272 (2 additions, 2 deletions, 1 files changed)
Branch: slaclab/htps-update

Notes:

Description

  • Required due to recent increase of AXI stream width from 512b to 1024b
  • Refer to #1247

VHDL Simulation Updates
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue May 6 12:00:32 2025 -0700
Pull: #1274 (179 additions, 47 deletions, 37 files changed)
Branch: slaclab/sim-testbed-clean-up

Notes:

Description

removing base/vhdl-libs
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue May 6 12:00:18 2025 -0700
Pull: #1275 (0 additions, 115752 deletions, 87 files changed)
Branch: slaclab/remove-copy-of-ieee-lib

Notes:

Description

  • Remove "copy" of IEEE VHDL that are not required
  • Toolchain copy of these library files should be used instead

More sim testbed clean up
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon May 12 12:12:35 2025 -0700
Pull: #1276 (1382 additions, 520 deletions, 90 files changed)
Branch: slaclab/more-sim-testbed-clean-up

Notes:

Description

corner case fix for AxiStreamPkg.vhd
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri May 16 09:51:08 2025 -0700
Pull: #1277 (2 additions, 2 deletions, 1 files changed)
Branch: slaclab/AxiStreamPkg-pathc

Notes:

Description

  • Prevent for loop being beyond the range of the tUser
  • Reminder that the loop is required (instead of setting the field directly) due to capability with Cadence Genus support

Sensitivity list fix in AxiStreamDepacketizer2
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri May 16 10:26:36 2025 -0700
Pull: #1279 (6 additions, 3 deletions, 2 files changed)
Branch: slaclab/sensitivity-list-fix

Notes:

Description

There is a bug in the emacs vhdl-mode sensitivity list generator that doesn't catch that crcOut is used in the process.
This is probably because its usage is buried in a procedure.
The signal has been manually added to the sensitivity list.

Assets 2
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Minor Release v2.59.0

30 Apr 23:12
@ruck314 ruck314
v2.59.0
df09072
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Minor Release v2.59.0

Pull Requests Since v2.58.0

Unlabeled

  1. #1270 - QSFP I2C Updates
  2. #1268 - adding more QSFP SW registers from SFF-8636 spec
  3. #1271 - Bug fix for protocols/i2c/rtl/I2cMaster.vhd

Pull Request Details

adding more QSFP SW registers from SFF-8636 spec
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Apr 25 14:30:52 2025 -0700
Pull: #1268 (799 additions, 20 deletions, 1 files changed)
Branch: slaclab/SFF-8636-updates

Notes:

Description

  • Specifically this branch is to get status and control of the CDR registers

QSFP I2C Updates
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Apr 29 16:30:56 2025 -0700
Pull: #1270 (932 additions, 636 deletions, 5 files changed)
Branch: slaclab/qsfp-fw-dsm-disable-cdr

Notes:

Description

  • This module used to periodically write CDR disable to the QSFP modules via AXI-Lite crossbar
  • The reason why this is not integrated into a AXI-Lite I2C Master endpoint is because the QSFP I2C access might be behind a I2C MUX and periodically updates with the I2C MUX context will cause collisions on the I2C bus

Bug fix for protocols/i2c/rtl/I2cMaster.vhd
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Apr 30 10:19:44 2025 -0700
Pull: #1271 (3 additions, 0 deletions, 1 files changed)
Branch: slaclab/i2c-txnError

Notes:

Description

  • Assert coreRst on i2c_master_byte_ctrl whenever a txnError event occurs.
  • Fixes a bug where, if an I2C device is removed (e.g., unplugging a QSFP module from its cage) and subsequently accessed, an error is correctly triggered. However, when the device is reconnected, the controller remains stuck in the error state. This change ensures proper recovery by resetting the controller on error.
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Minor Release v2.58.0

24 Apr 20:34
@ruck314 ruck314
v2.58.0
0ec59d6
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Minor Release v2.58.0

Pull Requests Since v2.57.0

Unlabeled

  1. #1259 - VHDL Beautify all of SURF VHDL files + script to automate the process
  2. #1261 - Adding VSG Linter
  3. #1251 - adding Ads54J54 software device support
  4. #1263 - adding coaxpress.PhantomS641 support
  5. #1255 - Vivado XSIM 2024.2 bug fix
  6. #1257 - rebuilding all the XVC .DCP for 1024b AXI stream
  7. #1252 - RSSI Updates
  8. #1267 - misc python for f-strings formatting
  9. #1262 - AxiStreamRingBuffer: adding dataStateIdx & trigStateIdx registers
  10. #1260 - adding PrintStatus() local command for use in notebooks
  11. #1256 - Vivado 2024.2 bug fix for generating AxiStreamFifoV2.fifoWriteUser
  12. #1253 - DMA write timeout issue resolved
  13. #1266 - Fixed matrix shape check in sugoi pixel matrix config
  14. #1265 - Update _Max5443.py
  15. #1264 - Fixed missing import in init.py
  16. #1258 - Require a minimum Rogue version

Pull Request Details

adding Ads54J54 software device support
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Apr 15 12:38:31 2025 -0700
Pull: #1251 (918 additions, 0 deletions, 2 files changed)
Branch: slaclab/ads54j54

Notes:

Description

Deps

This PR will depend on the following rogue software PRs/tags

Example of YAML load

Ads54J54:
  Reg:
    0x00: 0xA400 # 4wire, 2s complement, Decimation filter enabled, Low pass
    0x0D: 0x0000
    0x0D: 0x0202
    0x0D: 0x0303
    0x01: 0xAF7A
    0x02: 0x0000
    0x03: 0x4040
    0x04: 0x000F
    0x05: 0x0000
    0x06: 0xF7FF # Power down: Light sleep channel AB
    0x07: 0x0144
    0x08: 0x0144
    0x0C: 0x31E4
    0x0E: 0x0050 # Only enable DC0 & DD0
    0x0F: 0x0101 # 2 octets per frame
    0x10: 0x03E1 # 2 lanes for channel AB
    0x13: 0x0010 # HD=0, enable Scramble mode
    0x16: 0x0101 # 2 octets per frame
    0x17: 0x03E1 # 2 lanes for channel AB
    0x1A: 0x0010 # HD=0, enable Scramble mode
    0x1D: 0x0000
    0x1E: 0x0000
    0x1F: 0xFE50 # Power down: Lane DA[1:0], Lane DB[1:0], Lane DC1, Lane DD1, JESD PLL channel AB
    0x20: 0x0000
    0x21: 0x2000
    ```

RSSI Updates
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Apr 24 08:03:22 2025 -0700
Pull: #1252 (54 additions, 43 deletions, 7 files changed)
Branch: slaclab/rssi-local-busy-patch

Notes:

Description

DMA write timeout issue resolved
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Apr 9 18:01:57 2025 -0700
Pull: #1253 (4 additions, 1 deletions, 1 files changed)
Branch: slaclab/dmawrite_devel

Notes:

Corrects the timeout issue we have been seeing before returning the write descriptor

Description

Timeout would happen when the FSM waited for all the transactions to conclude before sending the write descriptor. It is resolved by incrementing the 'reqCount' when the metadata is sent. It now matches the 'ackCount' and timeout is fixed.

Vivado XSIM 2024.2 bug fix
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Apr 15 12:38:59 2025 -0700
Pull: #1255 (236 additions, 236 deletions, 5 files changed)
Branch: slaclab/RstSync-vivado-2024.2-sim

Notes:

Description

  • Change RELEASE_DELAY_G upper bound from positive'high to (2**24), which resolved this XSIM error message
ERROR: [VRFC 10-3667] range extends beyond constraint of type 'integer_32' [.../submodules/surf/base/sync/rtl/RstSync.vhd:31]

Vivado 2024.2 bug fix for generating AxiStreamFifoV2.fifoWriteUser
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Apr 15 12:39:14 2025 -0700
Pull: #1256 (4 additions, 5 deletions, 1 files changed)
Branch: slaclab/axiStreamGetUserField-vivado-2024.2

Notes:

Description

  • This change wraps the resize(axiStreamGetUserField(...)) assignment in a generate block that only activates when FIFO_USER_BITS_C > 0.
  • This avoids generating logic for a zero-width TUSER field, which caused a segmentation fault during Vivado 2024.2 synthesis.

rebuilding all the XVC .DCP for 1024b AXI stream
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Apr 15 12:38:47 2025 -0700
Pull: #1257 (118 additions, 112 deletions, 15 files changed)
Branch: slaclab/UdpDebugBridgeWrapper-patch

Notes:

Description

  • Required due to recent increase of AXI stream width from 512b to 1024b
  • Refer to #1247

Require a minimum Rogue version
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Apr 18 09:20:30 2025 -0700
Pull: #1258 (1 additions, 0 deletions, 1 files changed)
Branch: slaclab/rogue-minversion

Notes:

Description

Set the minimum Rogue version to 6.1.0

Details

In 6.1.0 we changed it so that bitSize is no longer necessary for arrays.

            self.add(pr.RemoteVariable(
                name        = "Mem",
                description = "Memory Array",
                offset      = 0x0000,
                numValues   = nelms,
                valueBits   = 32,
                valueStride = 32,
                bitSize     = 32 * nelms, # This is no longer necessary
                bulkOpEn    = False,
            ))

But if it's not set, older rogue will default to bitSize=32 then fail.
Then the uses gets a cryptic (to them) error from inside library code they don't know.
When the real problem is just that they need to update rogue to match the version of surf they are using.

We could do this individually for each Rogue python file that needs it, but that seems difficult to manage.

VHDL Beautify all of SURF VHDL files + script to automate the process
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Apr 18 09:39:19 2025 -0700
Pull: #1259 (13811 additions, 13646 deletions, 461 files changed)
Branch: slaclab/beautify_vhdl

Notes:

Description

adding PrintStatus() local command for use in notebooks
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Apr 18 09:27:43 2025 -0700
Pull: #1260 (23 additions, 14 deletions, 1 files changed)
Branch: slaclab/AxiVersion-printStatus

Notes:

Description

  • Required to get the equivalent of the AxiVersion.printStatus() prints when using a VirtualClient

Adding VSG Linter
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Apr 23 14:20:56 2025 -0700
Pull: #1261 (4689 additions, 4206 deletions, 363 files changed)
Branch: slaclab/vsg-linter-dev

Notes:

Description

  • Used to enforcing VHDL coding style via CI

Important for Reviewer

  • In addition to review these linter fixes, we need to determine if we have configured vsg-linter.yml to be the "standard" that our VScode IDE should reference when developing.

AxiStreamRingBuffer: adding dataStateIdx & trigStateIdx registers
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Apr 23 07:51:26 2025 -0700
Pull: #1262 (51 additions, 1 deletions, 3 files changed)
Branch: slaclab/AxiStreamRingBuffer-state

Notes:

Description

  • Useful debugging registers to expose to know what the state of the two FSMs are

adding coaxpress.PhantomS641 support
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Apr 23 07:51:38 2025 -0700
Pull: #1263 (809 additions, 23 deletions, 4 files changed)
Branch: slaclab/cxpof-Phantom-S641

Notes:

Description

  • Migrated the information from the PhantomS641 XML file
  • Minor update to PhantomS991 that discovered during the the PhantomS641 register map writing

Fixed missing import in init.py
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Apr 21 17:51:50 2025 -0700
Pull: #1264 (1 additions, 0 deletions, 1 files changed)
Branch: slaclab/python-init-fix

Notes:

Description

The command for the minimum required rogue versio...

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Minor Release v2.57.0

31 Mar 22:27
@ruck314 ruck314
v2.57.0
6773235
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Minor Release v2.57.0

Pull Requests Since v2.56.0

Unlabeled

  1. #1244 - removing obsolete surf.xilinx._RfDataConverter python
  2. #1248 - Delete scripts/generateDocumentationAndDeploy.sh
  3. #1246 - Added DMA configurable timeout register
  4. #1250 - updating ruckus.tcl to be consistent
  5. #1249 - Update README.md to include DOE Code Reference
  6. #1247 - Update AxiStreamPkg.vhd from 512-bit to 1024-bit wide data bus support

Pull Request Details

removing obsolete surf.xilinx._RfDataConverter python
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Mar 14 15:58:20 2025 -0700
Pull: #1244 (0 additions, 629 deletions, 4 files changed)
Branch: slaclab/surf-rfdc-api-obsolete

Notes:

Description

Added DMA configurable timeout register
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Mar 31 12:24:04 2025 -0700
Pull: #1246 (23 additions, 8 deletions, 3 files changed)
Branch: slaclab/add_timeout

Notes:

Added configurable timeout register to acknowledge the timeout

Description

Added a configurable timeout register which was earlier hardcoded. If timeout reg value is reached before the write transactions are completed, the descriptor is returned.

Update AxiStreamPkg.vhd from 512-bit to 1024-bit wide data bus support
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Mar 24 11:48:26 2025 -0700
Pull: #1247 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/AxiStreamPkg-1024b

Notes:

Description

  • Not ideal because in simulation the unused bits doe not get optimized away.
  • However, I am working with a user than needs a 1024-bit wide AXI stream data bus.

Delete scripts/generateDocumentationAndDeploy.sh
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Mar 24 11:48:53 2025 -0700
Pull: #1248 (0 additions, 136 deletions, 1 files changed)
Branch: slaclab/generateDocumentationAndDeploy-removal

Notes:

Description

Update README.md to include DOE Code Reference
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Mar 24 11:48:41 2025 -0700
Pull: #1249 (2 additions, 0 deletions, 1 files changed)
Branch: slaclab/ruck314-patch-1

Notes:

Description

  • Good practice to cite this reference in the README

updating ruckus.tcl to be consistent
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Mar 31 11:54:36 2025 -0700
Pull: #1250 (4 additions, 4 deletions, 4 files changed)
Branch: slaclab/ruckus-proc-load

Notes:

Description

  • updating remaining ruckus.tcl files to use the more portable version of loading proc
  • Required for non-Vivado projects to load the SURF source code into their IDE software
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Minor Release v2.56.0

04 Mar 02:44
@ruck314 ruck314
v2.56.0
b42ea0e
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Minor Release v2.56.0

Pull Requests Since v2.55.0

Unlabeled

  1. #1239 - Update surf_ci.yml to check for tabs
  2. #1236 - Adding AxiRingBuffer
  3. #1237 - migrating CI from ubuntu-22.04 to ubuntu-24.04
  4. #1240 - Bug fix for the PGPv3's and PGPv4's AXI-Lite crossbar with respect to DRP interface
  5. #1238 - Fix PGP2FC Bug - Don't allow Fast Control RX when link is not up
  6. #1243 - check for AXI_CONFIG_G.ADDR_WIDTH_C <= 40 in AxiStreamDmaV2Desc.vhd

Pull Request Details

Adding AxiRingBuffer
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Feb 24 08:56:31 2025 -0800
Pull: #1236 (1155 additions, 2 deletions, 6 files changed)
Branch: slaclab/AxiRingBuffer

Notes:

Description

  • Similiar to the AxiStreamRingBuffer module, but uses a AXI4 memory interface (instead of BRAM/URAM) for the ring buffering.
  • This module will enable the users to have larger buffers than what's supported with BRAM/URAM (e.g. DDR, HBM, etc)

migrating CI from ubuntu-22.04 to ubuntu-24.04
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Feb 24 09:44:29 2025 -0800
Pull: #1237 (3 additions, 28 deletions, 2 files changed)
Branch: slaclab/github-ci/ubuntu-24.04

Notes:

Description

  • Newer versions of Ubuntu support installing ghdl via apt, eliminating the need for manual installation.

Fix PGP2FC Bug - Don't allow Fast Control RX when link is not up
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Mon Feb 24 10:06:23 2025 -0800
Pull: #1238 (2 additions, 2 deletions, 1 files changed)
Branch: slaclab/pgpfc-fix

Notes:

Description

The Fast Control word RX logic was not checking to make sure the link was even up before outputting FC words. This caused disconnected links to output FC words fairly often from random input patterns.

The fix is to hold the entire FC RX logic in reset of the link is not up.

Update surf_ci.yml to check for tabs
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Feb 24 12:10:05 2025 -0800
Pull: #1239 (3133 additions, 3100 deletions, 17 files changed)
Branch: slaclab/team-never-tabs

Notes:

Description

  • Assert error in the workflow if there are tabs (instead of spaces)

Bug fix for the PGPv3's and PGPv4's AXI-Lite crossbar with respect to DRP interface
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Feb 17 20:37:49 2025 -0800
Pull: #1240 (4 additions, 4 deletions, 4 files changed)
Branch: slaclab/pgp4-gty-bug-fix

Notes:

Description

check for AXI_CONFIG_G.ADDR_WIDTH_C <= 40 in AxiStreamDmaV2Desc.vhd
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Mar 3 17:39:57 2025 -0800
Pull: #1243 (3 additions, 0 deletions, 1 files changed)
Branch: slaclab/AxiStreamDmaV2Desc-40b-address

Notes:

Description

  • Required because we ran out of bits to map the address from the FIFO:
v.dmaWrDescAck(i).address(63 downto 40) := (others => '0');
v.dmaWrDescAck(i).address(39 downto 4)  := wrFifoDout(63 downto 28);
v.dmaWrDescAck(i).address(3 downto 0)   := (others => '0');
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Minor Release v2.55.0

10 Feb 19:33
@ruck314 ruck314
v2.55.0
27a43e8
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Minor Release v2.55.0

Pull Requests Since v2.54.0

Unlabeled

  1. #1230 - RSSI diagnostic updates
  2. #1191 - Multiple entries ARP table
  3. #1229 - sy56040 clean up and adding sy89297
  4. #1231 - python/surf/devices/ti/_Adc32Rf45.py Updates
  5. #1235 - Ci whitespace checker
  6. #1233 - Updated FSM to latch meta data
  7. #1234 - git hash leading zero bug fix

Pull Request Details

Multiple entries ARP table
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Jan 27 09:14:19 2025 -0800
Pull: #1191 (1018 additions, 445 deletions, 6 files changed)
Branch: FilMarini/multi-arp

Notes:

Description

  • The file ethernet/UdpEngine/rtl/ArpIpTable.vhd contains a dynamic LUT which keeps in memory both IPs and MAC addressed. A new entry is memorized in the LUT every time a new 'clientRemoteIp' is detected
  • In the ethernet/UdpEngine/rtl/UdpEngineArp.vhd, every time the destination IP changes, the correspondent MAC address is either retrieved from the LUT if already memorized, or a new entry is created after an ARP request/response.
  • The IP/MAC LUT works as a circular buffer. Once the LUT is filled, then the first LUT address will be filled if a new unknown IP is given to the core
  • In the ethernet/UdpEngine/rtl/UdpEngineTx.vhd the incoming packets are checked for the tDest metadata field. If tDest /= 0, then the IP/MAC address saved in the tDest LUT address are used

Details

  • Currently the LUT is filled in order: first given IP is saved in position 1, second given IP is saved in position 2, and so on. Maybe its good to have a way to feed the ARP table from a file (like a JSON file for example) so the user has better control over the ARP table. I'm not sure, suggestions are welcome!
  • Also, what happens if the tDest field refers to an address that has not been filled? Currently I just flush the data (Or at least thats what I think its doing, havent tested it yet)
  • Also, emacs beautifier should be run with SLAC settings

sy56040 clean up and adding sy89297
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Jan 28 08:57:45 2025 -0800
Pull: #1229 (344 additions, 2 deletions, 7 files changed)
Branch: slaclab/Sy89297

Notes:

Description

RSSI diagnostic updates
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Feb 5 12:21:47 2025 -0800
Pull: #1230 (342 additions, 3413 deletions, 14 files changed)
Branch: slaclab/SmurfC1100FebEmu

Notes:

Description

python/surf/devices/ti/_Adc32Rf45.py Updates
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Feb 5 12:18:53 2025 -0800
Pull: #1231 (18 additions, 24 deletions, 3 files changed)
Branch: slaclab/smurf_v6

Notes:

Description

Updated FSM to latch meta data
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Feb 10 10:33:39 2025 -0800
Pull: #1233 (5 additions, 1 deletions, 1 files changed)
Branch: slaclab/mishra_dev43

Notes:

Description

Updated FSM to latch the meta data to the AXIS in AxiStreamDmaV2Write.vhd. The 'overflow' bit should now be available in the AXIS header.

git hash leading zero bug fix
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Feb 4 11:27:47 2025 -0800
Pull: #1234 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/githash-leading-zero

Notes:

Here's what the print would look like if there was a leading zero in the value:

GitHash      = 0x2a6000a172a68c0ad2e83f4b816701fd159603c

Here's what the print looks like with this path:

GitHash      = 02a6000a172a68c0ad2e83f4b816701fd159603c

Removed the 0x characters to make it easier to copy/paste into Github web browser UI for githash searching

Ci whitespace checker
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Feb 10 11:09:26 2025 -0800
Pull: #1235 (14 additions, 7 deletions, 5 files changed)
Branch: slaclab/ci-whitespace-checker

Notes:

Description

  • This will prevent users from merging trailing white spaces in their pull requests
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Minor Release v2.54.0

24 Jan 16:48
@ruck314 ruck314
v2.54.0
18a3556
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Minor Release v2.54.0

Pull Requests Since v2.53.0

Unlabeled

  1. #1225 - Event Frame Sequencer Protocol development
  2. #1227 - Bug fixes and Code Clean Up for xvc-udp
  3. #1222 - Misc. GT Clock outputs for the GTY+ ETH modules
  4. #1224 - Update LICENSE.txt
  5. #1221 - Added overflow bit to meta data

Pull Request Details

Added overflow bit to meta data
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Jan 6 11:28:47 2025 -0800
Pull: #1221 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/mishra_dev

Notes:

Description

Added the overflow bit to the meta data to check if the dma write buffer has overflowed.

Details

Added the overflow bit to the meta data. It is to be read by the 'aes-stream-drivers' to throw an error if the dma write buffer has overflowed.

Misc. GT Clock outputs for the GTY+ ETH modules
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Jan 1 01:21:32 2025 -0600
Pull: #1222 (4 additions, 1 deletions, 2 files changed)
Branch: slaclab/clocks-gty+

Notes:

Description

Update LICENSE.txt
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Jan 6 14:29:36 2025 -0800
Pull: #1224 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/ruck314-patch-1

Notes:

Description

  • Updating for CY2025

Event Frame Sequencer Protocol development
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Jan 23 08:56:00 2025 -0800
Pull: #1225 (1785 additions, 1 deletions, 10 files changed)
Branch: slaclab/EventFrameSequencerMux

Notes:

Description

This module draws inspiration from the AxiStream Batcher Protocol Version 1, which uses the AxiStreamBatcherEventBuilder.vhd. Unlike the original design, which creates a single super-frame per event, this module transmits event frames in a guaranteed sequence. As a result, each event consists of multiple frames, but the order of these frames within an event is always preserved.

In the AxiStreamBatcherEventBuilder.vhd, a super-header and multiple sub-frame tails are prepended or appended to the stream. In contrast, this module eliminates tail appending and instead prepends a header to each frame as it is forwarded through the sequencer. This header includes all the metadata necessary to reconstruct AXI stream sideband information on the receiver side, such as TDEST, TUSER_FIRST, and other relevant signals.

Documenation

Bug fixes and Code Clean Up for xvc-udp
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Jan 24 08:37:52 2025 -0800
Pull: #1227 (152 additions, 31 deletions, 46 files changed)
Branch: slaclab/xvc-2024.1

Notes:

Description

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Minor Release v2.53.0

06 Dec 16:37
@ruck314 ruck314
v2.53.0
60065b6
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Minor Release v2.53.0

Pull Requests Since v2.52.1

Bug

  1. #1166 - Bug Fixes and Enhancements from LDMX Project Development

Enhancement

  1. #1166 - Bug Fixes and Enhancements from LDMX Project Development

Unlabeled

  1. #1219 - Adding SACI Version 2
  2. #1209 - added RoCEv2 README

Pull Request Details

Bug Fixes and Enhancements from LDMX Project Development
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Dec 5 10:28:09 2024 -0600
Pull: #1166 (1899 additions, 246 deletions, 40 files changed)
Branch: slaclab/ldmx-dev
Labels: bug, enhancement

Notes:

Description

There are many small changes, mostly to fix issues found in simulation.

Details

  • AxiStreamResize
    • Better error reporting if generic assert fails
  • Ad9249ReadoutGroup2
    • Initialize signal to avoid unknowns in simulation
  • Ad9249Group (simulation)
    • Fix incomplete sensitivity list
  • Pgp2FcAxi
    • Apply TX FC bus from input to PGP block
  • PGP2FC GTY IP Core
    • Remove "project_parameters" from XCI file
    • Allows XCI to load with different US+ FPGAs
  • PGP2FC GTY IP Core Wrapper
    • Output rxPmaResetDone
      • Needed for external MMCM reset
    • Update resets based on simulation discoveries
    • Set freerun frequency to 185.71/2 MHz
  • Add GTH IP Core and wrapper for PGP2FC
  • ClockManagerUltraScale (Plus)
    • Resolve unknowns on DrpDo output from GT to zeros to avoid propagating them in simulation
  • GtRxAlignCheck
    • Use registered values for read-only AXI-Lite registers
    • Apply bug fix so resetErr only reset the FSM when resetDone is high
  • AxiLiteRingBuffer
    • Fix bugs in Rogue Device
  • Rogue Devices
    • Add several registers to the "NoConfig" group

added RoCEv2 README
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Dec 4 13:05:27 2024 -0600
Pull: #1209 (362 additions, 1 deletions, 3 files changed)
Branch: slaclab/RoCE-Readme

Notes:

Providing the RoCEv2 files with a README and a LICENSE file

Description

Added the README file to the RoCEv2 related folder. In the README I cite where the files come from, the fact that they have been generated from Bluespec SystemVerilog, the fact that they have been modified and the licensing conditions

Adding SACI Version 2
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Dec 5 10:57:17 2024 -0600
Pull: #1219 (1263 additions, 7 deletions, 45 files changed)
Branch: slaclab/saci2

Notes:

Description

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Patch Release v2.52.1

03 Dec 17:30
@ruck314 ruck314
v2.52.1
18541d2
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Description

Full Changelog: v2.52.0...v2.52.1

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Minor Release v2.52.0

03 Dec 16:14
@ruck314 ruck314
v2.52.0
cbb9800
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Minor Release v2.52.0

Pull Requests Since v2.51.0

Bug

  1. #1218 - Added strWrite() procedure to declaration section of TextUtilPkg

Unlabeled

  1. #1192 - Adding RoCEv2 support to the SURF Ethernet library
  2. #1212 - Big fixes for SgmiiDp83867LvdsUltraScale and Ultrascale+ operations
  3. #1216 - AxiStreamGearbox mod for Synopsys synth tool
  4. #1213 - CXPoF: TID VHDL Style Fix
  5. #1214 - Update to AxiStreamFrameRateLimiter.vhd
  6. #1207 - Hot Fix for CI: Removing C++ linter
  7. #1210 - Update ruckus.tcl with missing ad5541 load

Pull Request Details

Adding RoCEv2 support to the SURF Ethernet library
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Oct 14 09:51:41 2024 -0700
Pull: #1192 (69758 additions, 42 deletions, 108 files changed)
Branch: slaclab/EthMacCore-RoCEv2

Notes:

Description

Hot Fix for CI: Removing C++ linter
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Oct 7 14:26:59 2024 -0700
Pull: #1207 (3 additions, 3 deletions, 1 files changed)
Branch: slaclab/cpp-linter

Notes:

Description

  • remove all the linting for now since cpplint is really only for c++ files
  • We should find another linter for these pure C files

Update ruckus.tcl with missing ad5541 load
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Oct 21 16:24:14 2024 -0700
Pull: #1210 (1 additions, 0 deletions, 1 files changed)
Branch: slaclab/ad5541-missing-ruckus-load

Notes:

Description

In the previous pull request for AD5541 one ruckus.tcl file was missed that prevents this module from being found properly.

Related

Big fixes for SgmiiDp83867LvdsUltraScale and Ultrascale+ operations
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Oct 24 08:42:45 2024 -0700
Pull: #1212 (173 additions, 134 deletions, 8 files changed)
Branch: slaclab/GigEthLvdsUltraScale+

Notes:

Description

CXPoF: TID VHDL Style Fix
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Oct 25 08:07:07 2024 -0700
Pull: #1213 (18 additions, 18 deletions, 7 files changed)
Branch: slaclab/CXPoF

Notes:

Description

  • generics should end in '_G' and not '_C'

Update to AxiStreamFrameRateLimiter.vhd
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Oct 28 08:08:58 2024 -0700
Pull: #1214 (12 additions, 2 deletions, 1 files changed)
Branch: slaclab/AxiStreamFrameRateLimiter

Notes:

Description

  • adding mAxisCtrl.pause support

AxiStreamGearbox mod for Synopsys synth tool
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Dec 2 21:29:12 2024 -0600
Pull: #1216 (33 additions, 14 deletions, 2 files changed)
Branch: slaclab/axiStreamGbox-asic-dev

Notes:

Synopsys tool (presto) failed to synthesize original version of this with the following error:

"Constant Value Required"

on all modified lines; obviously an issue with the slicing of the std_logic_vectors.

circumventing by performing bit-by-bit assignment

Added strWrite() procedure to declaration section of TextUtilPkg
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Sun Dec 1 11:21:04 2024 -0600
Pull: #1218 (4 additions, 1 deletions, 1 files changed)
Branch: rbrglez/issue/1217-TextUtilPkg
Labels: bug

Notes:

Description

In TextUtilPkg I added strWrite() to the declaration section of TextUtilPkg.

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