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Patch Release v2.25.2

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@ruck314 ruck314 released this 18 Nov 23:55
· 1640 commits to main since this release
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Pull Requests Since v2.25.1

Unlabeled

  1. #922 - Release Candidate v2.25.2
  2. #912 - MicroblazeBasicCore + Vivado 2021.2 bug fix
  3. #921 - Bug fixes for UartRx and Clink
  4. #915 - Use DSP Clock Enable to Stall Filter Pipeline
  5. #919 - Show hex and ascii in UP900 serial diagnostics
  6. #913 - Fix AxiStreamTap
  7. #917 - Pre release axistreamtap: fix type in MODE_G = PASSTRHOUGH
  8. #914 - ESSURF-20 - AxiStreamTap Mux Mode Fix

Pull Request Details

MicroblazeBasicCore + Vivado 2021.2 bug fix

Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Nov 1 12:50:15 2021 -0700
Pull: #912 (1654 additions, 468 deletions, 3 files changed)
Branch: slaclab/microblaze-2021.2

Notes:

Description

  • Required for resolving a .bd module version locking issue

Fix AxiStreamTap

Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Nov 3 13:36:31 2021 -0700
Pull: #913 (10 additions, 10 deletions, 1 files changed)
Branch: slaclab/essurf-19

Notes:

Description

AxiStreamDemux now evaluates routes from low index to high index. This broke AxiStreamTap as everything was being routed to index 0.

Details

JIRA

https://jira.slac.stanford.edu/browse/ESSURF-19

Related


ESSURF-20 - AxiStreamTap Mux Mode Fix

Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Nov 4 12:47:32 2021 -0700
Pull: #914 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/essurf-20

Notes:

Description

The output mux now uses MODE_G => "PASSTHROUGH" so as not to modify the incoming TDESTs.

JIRA

https://jira.slac.stanford.edu/browse/ESSURF-20

Related


Use DSP Clock Enable to Stall Filter Pipeline

Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Nov 8 16:06:51 2021 -0800
Pull: #915 (20 additions, 27 deletions, 2 files changed)
Branch: slaclab/fir-filter-opt

Notes:

Description

This change makes use the the DSP48 clock enable signal to stall the pipeline on cycles when it should not advance.

Previously, the design was synthesizing a set of stall registers and associated logic between each filter stage. Now it synthesizes a string of DSP48 blocks with no glue logic in between to create the filter.


Pre release axistreamtap: fix type in MODE_G = PASSTRHOUGH

Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Nov 9 08:35:47 2021 -0800
Pull: #917 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/pre-release-axistreamtap

Notes:

Description

AxiStreamTap.vhd U_MUX : MODE_G => "PASSTRHOUGH" becomes "PASSTHROUGH"


Show hex and ascii in UP900 serial diagnostics

Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Nov 16 19:47:37 2021 -0800
Pull: #919 (18 additions, 4 deletions, 1 files changed)
Branch: bhill-slac/Up900-diags

Notes:

Description

  • Show both hex and ascii output in UP900 serial diagnostics.

Bug fixes for UartRx and Clink

Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Nov 18 15:06:15 2021 -0800
Pull: #921 (319 additions, 85 deletions, 7 files changed)
Branch: slaclab/clink-dev

Notes:

Description

  • Fixed broken ClinkFramerTb simulation test bench
  • Added ClinkUartTb simulation test bench
  • bug fix to UartRx.vhd
  • bug fix to ClinkPkg.vhd
  • adding frameSize register to ClinkReg

Release Candidate v2.25.2

Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Nov 18 15:49:32 2021 -0800
Pull: #922 (2022 additions, 595 deletions, 14 files changed)
Branch: slaclab/pre-release
Issues: #912, #913, #914, #915, #917, #919, #921

Notes:

Description