As part of the Workshop VSD SoC Design Course.
As part of the lab introduction :
In the Process Design Kits (PDKs) the sky130A folder contains the libs.refs and lib.techs.
The libs.ref contains the different process folders. In each of these process we have the library (timing corners) , lef files, spice files, mag has the cells shape, the technology lef, the verilog folder has custom defined cell definition using primitive verilog syntax.
The libs.tech is the tools folder
Command Used :
- docker
- ./flow.tcl -interactive
- package require openlane 0.9
prep -design picorv32a
When above command is ran you can see the config.tcl used for configuration, PDK's root directory, Standard cell library, LEF files and Metal layers (Only 6 layers are avialble). Then Merging lef (Cell level lef and technology level lef).
The Synthesis stage generally takes input of the design files (Verilog files), Constraints and Standard cell library (.lib) to generate the Equivalent Logic Circuit.
Command used for yosys tool :
run_synthesis
Results after Synthesis Step is as follows :
The Chip area of the chip is 147712.918400.
The count of D-FF is 1613.
The synthesis netlist generated file as shown below :
The synthesis reports directory :
The variables defined for Floorplanning are as shown below :
The floorplan tcl script used for configuring the simulation.
run_floorplan
Opening the Magic Tool. The cirrent directory is in /results/floorplan
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/skylane130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def
s - Used to select the object.
v - center the Die.
what - dispalys the details of the object.
In below section shows the object of pins are routed in metal2.
All the logic blocks standard cells are placed in left side corner.
run_placement
After the command ran :
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/skylane130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def
Opening the Chip after run_placement stage
After every run the screenshot of the result is takenand stored. The View of chip afer this step done is as follws :
/home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/11-02_14-38/results/placement/picorv32a.placement.def.png
Placement of the Standard cells in Standard rows
magic -T sky130A.tech sky130_inv.mag &
Now we see the Layout of the Inverter. We see the following layers :
p-well
n-well
Gate of pmos and nmos are connected to Input pin.
Drain of pmos connected and Drain of nmos are shorted and connected to Output pin.
Source of pmos connected to VDD
Source of nmos connected to VGND
Polysilicon : Red line
By selecting usin keyboard key s and typing what in the console we see selected one is polysilicon layer. Connecting Gate of both nmos and pmos.
Similar for n-well.
The Technology LEF - It contains information about avialable metal layer via information DRC's of paticular technology used by placer and router etc.
Extracting the details form the layout, parasitics from the cell.
extract all
ext2spice cthresh 0 rthresh 0
ext2spice
After opening the extracted spice file.
Spice file sky130_inv.spice contents. Adding the pmos, nmos model files, Pulse and doing Transient analysis on the inverter.
Loading the skylane130_inv.spice file in ngspice tool.
The Input and Output Waveforms of Inverter
The basic tr Rise time calculation. 20% to 80% value changes.
The basic tpd Propogation delay. 50% of Output to 50% of input.
The basic tf Fall time calculation. 80% to 20% value changes.
In Day3 we designed our own Custom Cell from Circuit to Layout design of Inverter. In Magic tool the layout of Inverter was developed. We extracted the parasitics of the Inverter and dumped into spice file.
The reason is sometimes we do custom cell or group the standard cell and make a logic out of it. During Technology Mapping stage i.e., mapping logic to Standard cells. That is Logic Synthesis and Physical Synthesis step we tend to include the custom designed cell and its layout (FRAM) into our design. Then we proceed further with our Physical Design flow.
When we open the pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd. We open the tracks.info file. For this skylane130A the technology node is 130nm and the Fab gives 6 Metal Layers i.e., li1, met1, met2, met3, met4 and met5. So, during routing stage the tool using these metal tracks for routing.
To explain or understand the concept for example :
- met1 X 0.17 0.34
- met1 Y 0.17 0.34
The Metal1 track has multiple lines in Horizontal and Vertical layers in chip. The pitch(distance between the two met1 layers in Horizontal and Vertical direction) is 0.34.
In below snippet it has offset and pitch values. Horizontal track is X and Vertical track Y.
Now using the li1 information and chnaging the grid information.
Dumping the lef file of the standard cell.
Next step is to plug this lef file to our design. We copy the file and move to src directory.
Now when we open anyone of our lib file. We see following table
For timing we have tr, tf and tpd. The chacterization table for each pin and the details.
For doing STA analysis we generally use the concept of Multi Mode and Multi Corner (MMMC). In our case we have
- skylane130_fd_sc_hd__typical.lib : skylane130_fd_sc_hd__tt_025C_1v80.
- skylane130_fd_sc_hd__slow.lib : skylane130_fd_sc_hd__ss_100C_1v60
- skylane130_fd_sc_hd__fast.lib : skylane130_fd_sc_hd__ff_n40C_1v95
For example the skylane130_fd_sc_hd__<nmos,pmos>.
Copying all the library files to design src folder.
Now we have lef and timing definition library files included in this.
Updated config.tcl file :
Inclusion of Custom cell :
Give feedback to Logic team to reduce as much as possible because once if you do floorplan, placement. Reduce the setup as much as possible. Next after CTS we will have setup and hold violation also. Make a note of all the fixes sent to folks and send in mail. Add commands also in the mail it becomes easy for them to take in fixes.
Again, after Routing. The Routing is iterative process again and again it will be done. The fixes can be same(repeated) or different. Sometimes fixes are taken in and some times they are missed. Check with previous reports to newly generated ones. Make a note of all the fixes sent to PnR folks and send in mail. Add commands also in mail it becomes easy for them to take in fixes.
Next Dump Verilog file :
In the Clock path we have separate Clk Buffer or Clk Inverter cells placed. We have X or H tree from theory in practical or in projects this will be different a little bit. Now in CTS stage onwards will have to focus on Hold time as we did for Setup time. So, many times the fixes given for setup might help or worse the Hold time if path is common.
In below screenshot you can see the list of cell included are shown below :
Because the clk path needs to have tr = tf. There needs not be any degradation of the signal on the clk path.
In CTS insertion of clock cells happen and new netlist is generated.
Loading from CTS stage we read LEF, DEF, DB and Verilog file.
At the end of routing we have following def file creation :
