Curated list of notes, books and other resources for the student of Nepal College of Information and Technology(NCIT) - Pokhara University, Nepal
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Updated
Sep 19, 2024 - HTML
Curated list of notes, books and other resources for the student of Nepal College of Information and Technology(NCIT) - Pokhara University, Nepal
Logic Circuits from the Juice library
Discover and create logic circuits
ViPeR 32-bit Pipelined RISC-V CPU
A continuation of the original Logisim circuit simulator by Carl Burch.
Materials for the Computer Science course, Digital Design (Logic Circuits)
Embedded domain-specific combinator library for the abstract assembly and automated synthesis of logical circuits.
SketchLogic is a Full-stack Logic Circuit Metadata Detector powered by a custom-trained YOLO model and some cool wire detection algorithms
Simple 6502 / 65C02 implementation
Analyze images of digital logic circuit schemes and automatically generate their truth tables.
This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.
A repository for Logic Circuits course in Amirkabir University of Technology
Logic Circuit module Implementation with Verilog
Gate-level implementation of a full-adder using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.
| Fundamentos de Sistemas Computacionais | Sergio Johann Filho | 2º | 2022/2 | 7.6 | 98800-04 | 60 |
🐙 Proteus-tools offers SPICE simulation, PCB design, firmware debugging, and IoT prototyping for professional engineers and open-source learners.
Logic expression normalization is an important step to reduce the original expression into a canonical normal form with fewer number of terms and operations. This way, the same expression can be implemented using fewer logic gates which means higher reliability and lower manufacturing cost
Gate-level implementation of a half-subtractor using Verilog, featuring a comprehensive testbench, truth table validation, and waveform analysis for beginners in digital design.
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