UART Module (Verilog)

This repository contains a Verilog implementation of a UART (Universal Asynchronous Receiver/Transmitter) module designed for serial communication. It supports 8-bit data transmission with a parity bit and a single stop bit. The default baud rate for transmission is set to 9600 bps.

Features

• UART Receiver and Transmitter
• 8-bit data width
• Parity bit generation and checking
• Single start and stop bit handling
• valid_out signal indicates when received data is valid

Interface

Inputs

• clk: Clock signal
• rst: Asynchronous reset
• rx: Serial data input
• tx_data[7:0]: Byte to be transmitted
• tx_enable: Enable signal for transmission

Outputs

• tx: Serial data output
• rx_data[7:0]: Received data byte
• valid_out: High when a valid byte has been received with correct parity
• done: Transmission completion indicator (can be extended)

States

Both receiver and transmitter use a simple FSM (Finite State Machine) with the following states:

• START: Start bit detection/transmission
• DATA: 8-bit data reception/transmission more pair_bit
• STOP: Stop bit reception/transmission

Notes

• The module calculates parity using XOR (^) for even parity.
• Reception begins on a falling edge (rx == 0) indicating a start bit.
• Transmission starts when rx_enable is asserted.

Todo List

• Add parameterization for baud rate to support multiple communication speeds.
• Include a parameter to enable or disable the parity bit.
• Add a parameter to select parity type (even or odd) when the parity bit is enabled.
• Introduce a parameter to configure the number of stop bits (1 or 2).
• Update the testbench to validate the new parameterized configurations.
• Verify synthesis compatibility for different parameter settings.
• Document the parameter usage and default values in the README.

License

This project is licensed under the MIT License.