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@sswetha18 sswetha18 commented Nov 11, 2025

This commit introduces support for Intel Wildcat Lake (WCL) enabling Zephyr RTOS to run on this platform. New additions include complete board definition and configuration, SoC support for the Wildcat Lake platform, device tree definitions and CPU bindings, GPIO driver extensions, and test overlays for peripheral validation.

@sswetha18 sswetha18 changed the title Wcl board def boards: intel: Add WCL board support Nov 11, 2025
@sswetha18 sswetha18 force-pushed the wcl_board_def branch 2 times, most recently from 5aa79e2 to 5e317b2 Compare November 11, 2025 15:53
@sswetha18 sswetha18 marked this pull request as ready for review November 12, 2025 03:09
@zephyrbot zephyrbot added area: Boards/SoCs area: SPI SPI bus area: Devicetree Bindings area: UART Universal Asynchronous Receiver-Transmitter platform: X86 x86 and x86-64 area: GPIO area: Disk Access area: Tests Issues related to a particular existing or missing test platform: Intel Intel Corporation labels Nov 12, 2025
@sswetha18 sswetha18 force-pushed the wcl_board_def branch 2 times, most recently from 96a6002 to 37c84c5 Compare November 12, 2025 05:46
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PR should be split into multiple commits e.g. one for adding SoC, one for adding board

@sswetha18 sswetha18 force-pushed the wcl_board_def branch 2 times, most recently from f972748 to 64adf5a Compare November 12, 2025 10:48
@danieldegrasse
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Moving assignment to @nordicjm as this is primarily board changes, maybe this should be assigned to @edersondisouza since it is an intel board?

@sswetha18 sswetha18 force-pushed the wcl_board_def branch 3 times, most recently from 30cf465 to 18b8215 Compare November 14, 2025 15:45
@sswetha18 sswetha18 requested a review from nordicjm November 14, 2025 16:07
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Board files OK but commits need reordering, you cannot add a board if the SoC etc. files are missing, things must be added in order and each commit should work independently without throwing errors

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Board files OK but commits need reordering, you cannot add a board if the SoC etc. files are missing, things must be added in order and each commit should work independently without throwing errors

I have reordered the commits

@sswetha18 sswetha18 requested a review from nordicjm November 17, 2025 15:06
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Board files OK but commits need reordering, you cannot add a board if the SoC etc. files are missing, things must be added in order and each commit should work independently without throwing errors

I have reordered the commits

Subsequent commits, including overlays, will compile successfully only after the base commits—SoC, board definition, and DTS—are merged.

This commit introduces SOC support for
Wildcat Lake.

Signed-off-by: S Swetha <s.swetha@intel.com>
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sswetha18 commented Nov 17, 2025

@nordicjm @dcpleung @andyross @tbursztyka @edersondisouza @kartben Please Review this PR

nordicjm
nordicjm previously approved these changes Nov 19, 2025
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minor nit observed.

This commit introduces board defintion for Wildcat Lake.

Signed-off-by: S Swetha <s.swetha@intel.com>
This commit introduces device treee source and yaml
for Wildcat Lake platform

Signed-off-by: S Swetha <s.swetha@intel.com>
This commit introduces overlay files for intel
Wildcat lake boards

Signed-off-by: S Swetha <s.swetha@intel.com>
Swap PAD_CFG1_IOSTERM_PU and PAD_CFG1_IOSTERM_PD values.

Signed-off-by: S Swetha <s.swetha@intel.com>
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sswetha18 commented Nov 19, 2025

@tejlmand Applied the suggested changes

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It seems some patch ordering issues are still here, otherwise looks good.


#define DT_DRAM_SIZE DT_SIZE_M(2048)

#include <intel/wildcat_lake.dtsi>
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This is included in this commit, but the file is available only on the next patch... shouldn't the next patch be brought before this one - or squashed here?


clock-frequency:
type: int
required: true
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This is required in this patch, but will be dropped on the next. So this change probably belongs to the next patch, which should be brought before this one.

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area: Boards/SoCs area: Devicetree Bindings area: Disk Access area: GPIO area: SPI SPI bus area: Tests Issues related to a particular existing or missing test area: UART Universal Asynchronous Receiver-Transmitter platform: Intel Intel Corporation platform: X86 x86 and x86-64

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6 participants