boards: intel: Add WCL board support

boards/intel/wcl/CMakeLists.txt

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Create an EFI image
+if(CONFIG_BUILD_OUTPUT_EFI)
+  set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+  COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py
+  -c ${CMAKE_C_COMPILER}
+  -o ${CMAKE_OBJCOPY}
+  -i ${ZEPHYR_BASE}/include ${PROJECT_BINARY_DIR}/include/generated
+  -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf
+  $<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--verbose>
+  WORKING_DIRECTORY ${PROJECT_BINARY_DIR}
+)
+endif()

boards/intel/wcl/Kconfig.defconfig

@@ -0,0 +1,70 @@
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BUILD_OUTPUT_STRIPPED
+	default y
+
+config MP_MAX_NUM_CPUS
+	default 2
+
+# The APIC TSC deadline and one-shot timers on this board run at 2 GHz; the HPET runs at 19.2 MHz.
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if APIC_TSC_DEADLINE_TIMER
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if APIC_TIMER_TSC
+	default $(dt_node_int_prop_int,/soc/hpet@fed00000,clock-frequency)
+
+if APIC_TIMER
+
+config APIC_TIMER_IRQ
+	default 24
+
+endif
+
+if APIC_TIMER_TSC
+
+config APIC_TIMER_TSC_M
+	default 2
+
+config APIC_TIMER_TSC_N
+	default 68
+
+endif
+
+config ACPI
+	default y
+
+if ACPI
+
+config HEAP_MEM_POOL_ADD_SIZE_ACPI
+	default 64000000
+
+config MAIN_STACK_SIZE
+	default 320000
+
+if SHELL
+
+config SHELL_STACK_SIZE
+	default 320000
+
+endif # SHELL
+
+endif # ACPI
+
+if DMA
+
+config DMA_64BIT
+	default y
+
+config DMA_DW_HW_LLI
+	default n
+
+config DMA_DW_CHANNEL_COUNT
+	default 2
+
+endif
+
+config UART_NS16550_INTEL_LPSS_DMA
+	default y if $(dt_nodelabel_enabled,uart0_dma) || $(dt_nodelabel_enabled,uart1_dma)
+
+config HAS_COVERAGE_SUPPORT
+	default y

boards/intel/wcl/Kconfig.intel_wcl_crb

@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_INTEL_WCL_CRB
+	select SOC_WILDCAT_LAKE

boards/intel/wcl/board.cmake

@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_set_flasher_ifnset(misc-flasher)
+board_finalize_runner_args(misc-flasher)

boards/intel/wcl/board.yml

@@ -0,0 +1,5 @@
+boards:
+  - name: intel_wcl_crb
+    vendor: intel
+    socs:
+      - name: wildcat_lake

boards/intel/wcl/doc/index.rst

@@ -0,0 +1,55 @@
+.. zephyr:board:: intel_wcl_crb
+
+Overview
+********
+Wildcat lake processor is a 64-bit multi-core processor.
+
+Wildcat Lake is based on a Hybrid architecture, utilizing P-cores E-cores Xe3 cores
+for performance and efficiency.
+
+For more information about Wildcat Lake Processor lines, P-cores, and E-cores
+please refer to `INTEL_WCL`_.
+
+This board configuration enables kernel support for the Wildcat Lake boards.
+
+Hardware
+********
+
+.. zephyr:board-supported-hw::
+
+General information about the board can be found at the `INTEL_WCL`_. website.
+
+Connections and IOs
+===================
+
+Refer to the `INTEL_WCL`_. website for more information.
+
+Programming and Debugging
+*************************
+Use the following procedures for booting an image for an Wildcat Lake RVP  board.
+
+.. contents::
+   :depth: 1
+   :local:
+   :backlinks: top
+
+Build Zephyr application
+========================
+
+#. Build a Zephyr application; for instance, to build the ``hello_world``
+   application for Wildcat Lake RVP:
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/hello_world
+      :board: intel_wcl_crb
+      :goals: build
+
+   .. note::
+
+      A Zephyr EFI image file named :file:`zephyr.efi` is automatically
+      created in the build directory after the application is built.
+
+.. include:: ../../../intel/common/efi_boot.rst
+   :start-after: start_include_here
+
+.. _INTEL_WCL: https://edc.intel.com/content/www/us/en/secure/design/confidential/products/platforms/details/wildcat-lake-processor-external-design-specification-volume-1-of-2/

boards/intel/wcl/intel_wcl_crb.dts

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2025 Intel Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <mem.h>
+
+#define DT_DRAM_SIZE            DT_SIZE_M(2048)
+
+#include <intel/wildcat_lake.dtsi>
+
+/ {
+	model = "intel_wcl_crb";
+	compatible = "intel,wildcat-lake-crb";
+
+	chosen {
+		zephyr,sram = &dram0;
+		zephyr,console = &uart_legacy;
+		zephyr,shell-uart = &uart_legacy;
+	};
+
+	aliases {
+		watchdog0 = &tco_wdt;
+		rtc = &rtc;
+		i2c-0 = &i2c0;
+		pwm-test = &pwm0;
+	};
+};
+
+&uart_legacy {
+	status = "okay";
+};
+
+&rtc {
+	status = "okay";
+};
+
+&smbus0 {
+	status = "okay";
+};
+
+&tco_wdt {
+	status = "okay";
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&hpet {
+	status = "okay";
+};
+
+&tgpio {
+	status = "okay";
+};

boards/intel/wcl/intel_wcl_crb.yaml

@@ -0,0 +1,20 @@
+identifier: intel_wcl_crb
+name: Wildcat Lake CRB
+type: mcu
+arch: x86
+toolchain:
+  - zephyr
+ram: 2048
+supported:
+  - acpi
+  - smp
+  - smbus
+  - watchdog
+  - rtc
+  - gpio
+  - pwm
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+vendor: intel

boards/intel/wcl/intel_wcl_crb_defconfig

@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_PIC_DISABLE=y
+CONFIG_LOAPIC=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_NS16550=y
+CONFIG_UART_NS16550_VARIANT_NS16750=y
+CONFIG_UART_CONSOLE=y
+CONFIG_X2APIC=y
+CONFIG_SMP=y
+CONFIG_BUILD_OUTPUT_EFI=y

drivers/gpio/gpio_intel.c

@@ -68,8 +68,8 @@
 #define PAD_CFG1_IOSTERM_MASK		(0x03 << PAD_CFG1_IOSTERM_POS)
 #define PAD_CFG1_IOSTERM_FUNC		(0 << PAD_CFG1_IOSTERM_POS)
 #define PAD_CFG1_IOSTERM_DISPUD		(1 << PAD_CFG1_IOSTERM_POS)
-#define PAD_CFG1_IOSTERM_PU		(2 << PAD_CFG1_IOSTERM_POS)
-#define PAD_CFG1_IOSTERM_PD		(3 << PAD_CFG1_IOSTERM_POS)
+#define PAD_CFG1_IOSTERM_PD		(2 << PAD_CFG1_IOSTERM_POS)
+#define PAD_CFG1_IOSTERM_PU		(3 << PAD_CFG1_IOSTERM_POS)
 
 #define PAD_CFG1_TERM_POS		10
 #define PAD_CFG1_TERM_MASK		(0x0F << PAD_CFG1_TERM_POS)

dts/bindings/cpu/intel,wildcat-lake.yaml

@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel Wildcat Lake CPU
+
+compatible: "intel,wildcat-lake"
+
+include: cpu.yaml

dts/bindings/timer/intel,hpet.yaml

@@ -14,6 +14,10 @@ properties:
   interrupts:
     required: true
 
+  clock-frequency:
+    type: int
+    description: HPET timer clock frequency in Hz
+
   no-legacy-irq:
     type: boolean
     description: Do not set legacy IRQ bit