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Releases: slaclab/surf

Minor Release v2.35.0

19 Oct 19:48
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v2.35.0
ba30e39
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Minor Release v2.35.0

Pull Requests Since v2.34.3

Unlabeled

  1. #1016 - Adding CoaXPress and CoaXPress-over-Fiber Support
  2. #1007 - Add Si570 PyRogue Device
  3. #1018 - Update FifoMux.vhd

Pull Request Details

Add Si570 PyRogue Device
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Wed Oct 19 12:25:39 2022 -0700
Pull: #1007 (243 additions, 1 deletions, 2 files changed)
Branch: slaclab/si570

Notes:

Description

Add a PyRogue Device class for the Si570 programmable clock chip found on the Alveo PCIe card and others.

Adding CoaXPress and CoaXPress-over-Fiber Support
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Oct 5 10:27:39 2022 -0700
Pull: #1016 (10120 additions, 6 deletions, 39 files changed)
Branch: slaclab/CoaXPress

Notes:

Description

Update FifoMux.vhd
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Oct 17 15:12:32 2022 -0700
Pull: #1018 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/FifoMux-patch
Issues: #1017

Notes:

Description

  • Bug fix for FifoMux.vhd when RD_DATA_WIDTH_G < WR_DATA_WIDTH_G and rd_en is a pulse
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Patch Release v2.34.3

28 Sep 19:28
@ruck314 ruck314
v2.34.3
0484417
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Patch Release v2.34.3

Pull Requests Since v2.34.2

Bug

  1. #1009 - SSP Bug Fix - Allow exit from DATA_S state for auto frame mode

Enhancement

  1. #1013 - Enhancements for AD9681 ADC modules
  2. #1011 - Pgp2bGtx7VarLatWrapper Tweaks
  3. #1010 - SrpV3AxiLite - Expose FIFO address width as top level generic

Unlabeled

  1. #1004 - Updates to AxiStreamRingBuffer.vhd
  2. #1005 - SspLowSpeedDecoderReg.py register description Update
  3. #1006 - Fix broken writes in _AxiLiteMasterProxy.py
  4. #1014 - Update _AxiVersion.py

Pull Request Details

Updates to AxiStreamRingBuffer.vhd
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Sep 13 17:02:05 2022 -0500
Pull: #1004 (56 additions, 66 deletions, 2 files changed)
Branch: slaclab/AxiStreamRingBuffer-extTrig

Notes:

Description

  • simplifying for external triggering

SspLowSpeedDecoderReg.py register description Update
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Sep 12 11:39:24 2022 -0500
Pull: #1005 (12 additions, 3 deletions, 1 files changed)
Branch: slaclab/SspLowSpeedDecoderReg-doc

Notes:

Description

  • Some of the registers were missing description fields

Fix broken writes in _AxiLiteMasterProxy.py
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Thu Sep 15 11:17:41 2022 -0700
Pull: #1006 (3 additions, 2 deletions, 1 files changed)
Branch: slaclab/proxy-fix

Notes:

Description

Write functionality has apparently been broken in the module for some time. We never realized it because everything we put on it is read only.

SSP Bug Fix - Allow exit from DATA_S state for auto frame mode
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Thu Sep 15 14:33:06 2022 -0700
Pull: #1009 (5 additions, 0 deletions, 1 files changed)
Branch: slaclab/ssp-auto-mode-fix
Issues: #828
Labels: bug

Notes:

Description

This module was rewritten in #828. This change left a bug, where the DATA_S state never exits when running with AUTO_FRAME_G=true. This bug has been fixed.

SrpV3AxiLite - Expose FIFO address width as top level generic
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Thu Sep 15 13:17:32 2022 -0700
Pull: #1010 (6 additions, 5 deletions, 1 files changed)
Branch: slaclab/srpv3-fifo-wdith-g
Labels: enhancement

Notes:

Description

The FIFO_ADDR_WIDTH_G generics for the TX and RX FIFOs in SrpV3AxiLite have been exposed as a module generic.
This is useful for applications that might benefit from smaller or larger SRP stream FIFOs.
The default is 9, which is what it was fixed at before, so this should have no effect on existing code.

Pgp2bGtx7VarLatWrapper Tweaks
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Thu Sep 15 14:32:46 2022 -0700
Pull: #1011 (54 additions, 49 deletions, 1 files changed)
Branch: slaclab/pgp-gtx7-tweaks
Labels: enhancement

Notes:

Description

  • Pass SIM generics up
  • Add BUFG on MMCM FB
    • RTL sim doesn't lock otherwise, and doesn't hurt to have it

Enhancements for AD9681 ADC modules
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Thu Sep 15 14:57:02 2022 -0700
Pull: #1013 (922 additions, 105 deletions, 4 files changed)
Branch: slaclab/ad9681-dev
Labels: enhancement

Notes:

Description

  • Add Ad9681ReadoutManual module, which uses delays values set by the user (software) rather than the auto aligner.
  • Add INVERT_G and NEGATE_G generics to Ad9681Readout
  • Use adcBitClk(0) to clock both "halves" of the logic.
    • Using separate clocks caused timing problems.
  • Simulation module now has correct latency.
  • Update PyRogue Device classes.

Update _AxiVersion.py
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Sep 23 10:06:34 2022 -0700
Pull: #1014 (2 additions, 1 deletions, 1 files changed)
Branch: slaclab/AxiVersion-update

Notes:

Description

  • Hiding FpgaReload in the GUI to prevent accidental reboots of the FPGA when the user is trying to click on UserRst
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Patch Release v2.34.2

01 Sep 15:56
@ruck314 ruck314
v2.34.2
f9fea6d
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Patch Release v2.34.2

Pull Requests Since v2.34.1

Bug

  1. #1001 - Properly exit poll thread when stopping AxiLiteMasterProxy.py

Enhancement

  1. #987 - Enhancements to PRBS modules
  2. #1000 - update to StdRtlPkg.vhd

Unlabeled

  1. #1003 - Bug fix for ClinkFraming.vhd & whitespace clean up

Pull Request Details

update to StdRtlPkg.vhd
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Sep 1 00:28:20 2022 -0500
Pull: #1000 (2 additions, 0 deletions, 1 files changed)
Branch: slaclab/new-slv-array
Labels: enhancement

Notes:

Description

  • adding Slv512Array & Slv512VectorArray

Properly exit poll thread when stopping AxiLiteMasterProxy.py
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Sep 1 00:29:16 2022 -0500
Pull: #1001 (8 additions, 0 deletions, 1 files changed)
Branch: slaclab/axi-lite-proxy-fix
Labels: bug

Notes:

Description

AxiLiteMasterProxy spins up a thread to handle its transactions. This thread was not being stopped when the Root was stopped, leading the applications hanging open. This has been fixed.

JIRA

https://jira.slac.stanford.edu/browse/ESROGUE-515

Related

Bug fix for ClinkFraming.vhd & whitespace clean up
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Sep 1 10:31:58 2022 -0500
Pull: #1003 (54 additions, 42 deletions, 2 files changed)
Branch: slaclab/clink-deca-patch

Notes:

Description

Enhancements to PRBS modules
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Wed Aug 31 21:46:56 2022 -0700
Pull: #987 (337 additions, 311 deletions, 8 files changed)
Branch: slaclab/prbs-registers
Labels: enhancement

Notes:

Description

  • AxiStreamMon
    • Use statusRst to reset the min and max statistics.
    • Previously used axisRst.
    • Previously could not reset packet rate statistics.
  • SsiPrbsRateGen
    • Allow an asynchronous localClk input that runs internal logic.
    • Use only 8 bits of AXI-Lite address space instead of 12.
  • SsiPrbsRx/SsiPrbsTx
    • Remap AXI-Lite register space to use 8 address bits instead of 10.
    • Use "new" style AXI-Lite procedures from AxiLitePkg.
  • Software
    • Update with new register mappings for SsiPrbsRx and SsiPrbsTx.
    • Add useful LinkedVariables to SsiPrbsRateGen.

Details

We will need to discuss the changes in SsiPrbsRx and SsiPrbsTx. It should be fine as long as projects distribute software properly with their firmware. But it could happen that someone tries to use new SURF software to access PRBS modules on legacy firmware and then it wont work.

The extra address bits in the PRBS modules were becoming a problem in a project where many of these modules were instantiated. It was cumbersome to fit them all in the available address space on a PCIe project where you don't have the full 32 bits of address space for the firmware application.

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Patch Release v2.34.1

24 Aug 22:14
@ruck314 ruck314
v2.34.1
4ec94a5
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Patch Release v2.34.1

Pull Requests Since v2.34.0

Unlabeled

  1. #992 - Fixed broken Sgmii88E1111LvdsUltraScale & GigEthReg.py clean up
  2. #993 - adding Max5443
  3. #995 - adding Max5443.py
  4. #994 - Updates to Ad9249ReadoutGroup[UltraScale]
  5. #996 - updates to SugoiManager
  6. #998 - Bug fix for base/ram/ruckus.tcl

Pull Request Details

Fixed broken Sgmii88E1111LvdsUltraScale & GigEthReg.py clean up
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Aug 17 16:03:22 2022 -0700
Pull: #992 (680 additions, 610 deletions, 8 files changed)
Branch: slaclab/GigEthLvdsUltraScaleCore

Notes:

Description

  • Broken due to the major overhaul of SALT protocol
  • Sgmii88E1111LvdsUltraScale used for the KCU105's RJ45 Ethernet interface
  • And some GigEthReg.py code clean up

adding Max5443
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Aug 18 21:56:36 2022 -0700
Pull: #993 (311 additions, 0 deletions, 2 files changed)
Branch: slaclab/MAX5443

Notes:

Description

  • Migrated this code from epix-hr-core and made it more generalize for any number of chips

Updates to Ad9249ReadoutGroup[UltraScale]
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Aug 19 16:55:14 2022 -0700
Pull: #994 (15 additions, 18 deletions, 2 files changed)
Branch: slaclab/Ad9249ReadoutGroup
Issues: #1

Notes:

Description

  • bug fix for Ad9249ReadoutGroup[UltraScale] when USE_MMCME_G=false
    • Required to prevent PLIOBUF #1 DRC error
Inputs of IBUF/BUFGP instance DIFFINBUF_INST (in AdcClk_I_Ibufds macro) is not driven by port. This might lead to unplaceable/unroutable situation

ERROR: [DRC ADEF-911] SIM_DEVICE_arch_mismatch: When the netlist was initialized, the value of SIM_DEVICE on cell U_App/GEN_REAL.U_AdcMon/GEN_FAST_ADC[1].U_MonAdcReadout/U_FRAME_DESERIALIZER/U_ISERDESE3_master was changed from 'ULTRASCALE' to 'ULTRASCALE_PLUS' to match the current FPGA architecture. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.

adding Max5443.py
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Sun Aug 21 08:49:30 2022 -0700
Pull: #995 (46 additions, 0 deletions, 2 files changed)
Branch: slaclab/Max5443-python

Notes:

Description

  • Missing complimentary software for PR# 993

updates to SugoiManager
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Aug 22 20:36:52 2022 -0700
Pull: #996 (20 additions, 5 deletions, 2 files changed)
Branch: slaclab/SugoiManager

Notes:

Description

  • Set bypFirstBerDet default to 0x1
  • Reduced the lockingCntCfg default
  • Set TXN to 0x0 when gearboxAligned=0x0
  • Map the gearboxAligned (A.K.A. "Linkup") to software
  • updating timerConfig default

Bug fix for base/ram/ruckus.tcl
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Aug 24 16:14:04 2022 -0500
Pull: #998 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/xpm-dual-port-fifo-patch
Issues: #997

Notes:

Description

  • Bug fix for XPM true dual port FIFO using Vivado 2019.1
  • Addresses issue #997
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Minor Release v2.34.0

16 Aug 20:29
@ruck314 ruck314
v2.34.0
7f0b2f5
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Minor Release v2.34.0

Pull Requests Since v2.33.0

Unlabeled

  1. #986 - adding IGMPv2 support to surf.ethernet library
  2. #989 - Updates to support flake8 v5
  3. #990 - AxiLiteCrossbarI2cMux.vhd Update
  4. #985 - AxiStreamDmaV2Fifo.vhd Update

Pull Request Details

AxiStreamDmaV2Fifo.vhd Update
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Jul 6 16:06:52 2022 -0700
Pull: #985 (4 additions, 2 deletions, 1 files changed)
Branch: slaclab/AxiStreamDmaV2Fifo-update

Notes:

Description

  • adding support for RD_PEND_THRESH_G
  • Required for maximizing HBM AXI3 memory read throughput

adding IGMPv2 support to surf.ethernet library
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Jul 7 08:40:21 2022 -0700
Pull: #986 (440 additions, 94 deletions, 7 files changed)
Branch: slaclab/ESCORE-720
Jira: https://jira.slac.stanford.edu/issues/ESCORE-720

Notes:

Description

  • IGMP_G default is false to keep the FPGA resources the same for older projects
  • Support up to 8 Group Addresses

Traffic Example

  • IGMP Membership Query Message from CPU to FPGA
Frame 4: 42 bytes on wire (336 bits), 42 bytes captured (336 bits) on interface eth2, id 0
Ethernet II, Src: Solarfla_51:76:41 (00:0f:53:51:76:41), Dst: Stanford_00:00:00 (08:00:56:00:00:00)
Internet Protocol Version 4, Src: 192.168.2.1, Dst: 192.168.2.10
    0100 .... = Version: 4
    .... 0101 = Header Length: 20 bytes (5)
    Differentiated Services Field: 0x00 (DSCP: CS0, ECN: Not-ECT)
    Total Length: 28
    Identification: 0x0001 (1)
    Flags: 0x0000
    Fragment offset: 0
    Time to live: 1
    Protocol: IGMP (2)
    Header checksum: 0x3484 [validation disabled]
    [Header checksum status: Unverified]
    Source: 192.168.2.1
    Destination: 192.168.2.10
Internet Group Management Protocol
    [IGMP Version: 2]
    Type: Membership Query (0x11)
    Max Resp Time: 2.0 sec (0x14)
    Checksum: 0xeeeb [correct]
    [Checksum Status: Good]
    Multicast Address: 0.0.0.0
  • IGMPv2 Membership Report from FPGA to CPU
Frame 7: 60 bytes on wire (480 bits), 60 bytes captured (480 bits) on interface eth2, id 0
Ethernet II, Src: Stanford_00:00:00 (08:00:56:00:00:00), Dst: IPv4mcast_07:07:07 (01:00:5e:07:07:07)
Internet Protocol Version 4, Src: 192.168.2.10, Dst: 224.7.7.7
    0100 .... = Version: 4
    .... 0101 = Header Length: 20 bytes (5)
    Differentiated Services Field: 0x00 (DSCP: CS0, ECN: Not-ECT)
    Total Length: 28
    Identification: 0x7d50 (32080)
    Flags: 0x4000, Don't fragment
    Fragment offset: 0
    Time to live: 32
    Protocol: IGMP (2)
    Header checksum: 0x33cf [validation disabled]
    [Header checksum status: Unverified]
    Source: 192.168.2.10
    Destination: 224.7.7.7
Internet Group Management Protocol
    [IGMP Version: 2]
    Type: Membership Report (0x16)
    Max Resp Time: 0.0 sec (0x00)
    Checksum: 0x02f1 [correct]
    [Checksum Status: Good]
    Multicast Address: 224.7.7.7

Updates to support flake8 v5
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Aug 1 12:13:10 2022 -0700
Pull: #989 (31 additions, 31 deletions, 6 files changed)
Branch: slaclab/flake8

Notes:

Description

  • resolved 'E275 missing whitespace after keyword' flake8 errors

AxiLiteCrossbarI2cMux.vhd Update
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Aug 16 13:15:49 2022 -0700
Pull: #990 (35 additions, 7 deletions, 1 files changed)
Branch: slaclab/AxiLiteCrossbarI2cMux-update

Notes:

Description

  • adding i2cRstL output port support
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Minor Release v2.33.0

29 Jun 17:16
@ruck314 ruck314
v2.33.0
c2f3a13
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Minor Release v2.33.0

Pull Requests Since v2.32.0

Unlabeled

  1. #984 - adding AxiStreamDmaV2Fifo.vhd
  2. #974 - Enhancements to Pgp2bGtx7FixedLat
  3. #978 - adding SspLowSpeedDecoder8b10bWrapperTb.vhd
  4. #979 - Minor PGP2fc code cleanup
  5. #981 - Corrected a register offset in ads54j60.py
  6. #983 - Pgp2bGtx7FixedLat.vhd Update

Pull Request Details

Enhancements to Pgp2bGtx7FixedLat
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Tue May 17 14:56:33 2022 -0700
Pull: #974 (174 additions, 84 deletions, 3 files changed)
Branch: slaclab/pgp-fl

Notes:

Description

These changes make the GTX7 fixed-latency PGP more like the (working) GTP7 fixed-latency PGP.

Details

  • Add IO for TX clock PLL/MMCM.
  • Add generics to allow PLL or MMCM in Wrapper.
  • Add generics and logic for more flexible clock configurations.

adding SspLowSpeedDecoder8b10bWrapperTb.vhd
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Apr 26 14:27:03 2022 -0700
Pull: #978 (231 additions, 0 deletions, 2 files changed)
Branch: slaclab/SspLowSpeedDecoder8b10bWrapperTb

Notes:

Description

  • Used to regression test the encoder/decoder/gearboxAligner
  • Does not include moving data at this time (future upgrade), only IDLE words

Minor PGP2fc code cleanup
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Apr 26 15:01:38 2022 -0700
Pull: #979 (86 additions, 86 deletions, 11 files changed)
Branch: slaclab/pgp2fc-whitespace-removal

Notes:

Description

  • White space removal

Corrected a register offset in ads54j60.py
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Jun 21 11:33:55 2022 -0700
Pull: #981 (3 additions, 3 deletions, 1 files changed)
Branch: slaclab/ads54J60-king

Notes:

Corrected a register offset in ads54j60.py

Description

-Changed the offset of registers "PDN_BUFFER_CHB_0" and "PDN_BUFFER_CHA_0".
The offset of both register was changed from "(masterPage + (40x20))" to "(masterPage + (40x21))"
This was done because both register were pointing at the same memory space of 2 other registers "PDN_ADC_CHA_0" and "PDN_ADC_CHB"

-Changed the name of the register "PDN_ADC_CHB" to "PDN_ADC_CHB_0".
This was done to uniform the register names.

Pgp2bGtx7FixedLat.vhd Update
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Jun 29 10:07:02 2022 -0700
Pull: #983 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/whitespace-removal

Notes:

Description

  • whitespace removal

adding AxiStreamDmaV2Fifo.vhd
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Jun 29 10:07:14 2022 -0700
Pull: #984 (783 additions, 0 deletions, 3 files changed)
Branch: slaclab/AxiStreamDmaV2Fifo

Notes:

Description

  • AxiStreamDmaV2Fifo is a wrapper on the AxiStreamDmaV2 engine
  • AxiStreamDmaV2Fifo.vhd is similar to AxiStreamDmaFifo.vhd.
    • However AxiStreamDmaV2Fifo.vhd support interleaved TDEST and "continuous" buffer support
  • This module is general enough to put inline of the DMA's inbound AXI stream
  • The plan is to include this module to all the general purpose PGP PCIe builds if the PCIe hardware support on-board memory
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Minor Release v2.32.0

18 Apr 15:56
@ruck314 ruck314
v2.32.0
403c2a8
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Minor Release v2.32.0

Pull Requests Since v2.31.1

Unlabeled

  1. #962 - PGP2 FC (Fast Control)
  2. #976 - fixed major typo in protocols/sugoi
  3. #975 - AxiStreamFrameRateLimiter.vhd Update

Pull Request Details

PGP2 FC (Fast Control)
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Apr 7 11:15:20 2022 -0700
Pull: #962 (7285 additions, 0 deletions, 21 files changed)
Branch: slaclab/pgp2fc-dev

Notes:

Description

A PGP2 variant protocol that allows opcodes to be sent every cycle, for fixed latency delivery of triggers.

This hasn't been fully tested yet.

AxiStreamFrameRateLimiter.vhd Update
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Apr 11 09:07:30 2022 -0700
Pull: #975 (73 additions, 28 deletions, 2 files changed)
Branch: slaclab/AxiStreamFrameRateLimiter-dropping

Notes:

Description

  • adding backpressure feature to AxiStreamFrameRateLimiter.vhd
    • backpressure = 0x1: Assert back pressure upstream when rate throttling
    • backpressure = 0x0: Drop upstream frames when rate throttling

fixed major typo in protocols/sugoi
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Apr 18 08:50:06 2022 -0700
Pull: #976 (64 additions, 64 deletions, 7 files changed)
Branch: slaclab/sugoi-typo-fix

Notes:

Description

  • change sugio to sugoi
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Patch Release v2.31.1

25 Mar 15:53
@ruck314 ruck314
v2.31.1
01cd96e
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Patch Release v2.31.1

Pull Requests Since v2.31.0

Unlabeled

  1. #973 - AxiMicronP30Pkg.vhd Update + XPM ruckus.tcl fix
  2. #971 - pgp4/gtyUs+ updates

Pull Request Details

pgp4/gtyUs+ updates
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Mar 21 15:55:55 2022 -0700
Pull: #971 (8 additions, 0 deletions, 2 files changed)
Branch: slaclab/Pgp4GtyUs-updates

Notes:

Description

  • exposing STATUS_CNT_WIDTH_G & ERROR_CNT_WIDTH_G to top-level

AxiMicronP30Pkg.vhd Update + XPM ruckus.tcl fix
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Mar 25 08:38:19 2022 -0700
Pull: #973 (14 additions, 2 deletions, 2 files changed)
Branch: slaclab/AxiMicronP30Pkg

Notes:

Description

  • adding useful constants into the package
  • Fixed base/ram/ruckus.tcl for older versions of Vivado
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Minor Release v2.31.0

17 Mar 00:40
@ruck314 ruck314
v2.31.0
1b4d452
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Minor Release v2.31.0

Pull Requests Since v2.30.1

Unlabeled

  1. #967 - Adding Amphenol LEAP Transceiver
  2. #968 - Adding SI5394 I2C Device Support
  3. #969 - Update Pgp3GtyUsQpll.vhd
  4. #966 - ruckus.tcl bug fix for SALT + Versal

Pull Request Details

ruckus.tcl bug fix for SALT + Versal
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Mar 9 14:12:23 2022 -0800
Pull: #966 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/Versal-dev

Notes:

Description

  • SALT does not support Versal yet

Adding Amphenol LEAP Transceiver
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Mar 14 15:26:33 2022 -0700
Pull: #967 (1732 additions, 0 deletions, 9 files changed)
Branch: slaclab/Amphenol-LeapXcvr

Notes:

Description

  • Adding the FW/SW to support this new 300 Gb/s transceiver (12 lanes x 25Gb/s/lane)

Adding SI5394 I2C Device Support
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Mar 16 16:55:22 2022 -0700
Pull: #968 (802 additions, 0 deletions, 8 files changed)
Branch: slaclab/SI5394-i2c

Notes:

Description

  • Required for Alveo U55C and C1100 data center PCIe cards

Update Pgp3GtyUsQpll.vhd
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Mar 16 16:55:34 2022 -0700
Pull: #969 (5 additions, 4 deletions, 1 files changed)
Branch: slaclab/ruck314-patch-1

Notes:

Description

  • Exposing QPLL_REFCLK_SEL_G has top-level generic such that gtGRefClk (QPLL_REFCLK_SEL_G="111") can be used
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Patch Release v2.30.1

09 Mar 03:51
@ruck314 ruck314
v2.30.1
0ec145a
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Patch Release v2.30.1

Pull Requests Since v2.30.0

Unlabeled

  1. #964 - Boxcar Integrator: Bug Fixes

Pull Request Details

Boxcar Integrator: Bug Fixes
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Mar 8 16:10:16 2022 -0800
Pull: #964 (16 additions, 4 deletions, 2 files changed)
Branch: slaclab/BoxcarIntegrator-debug

Notes:

Description

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