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Releases: slaclab/surf

Minor Release v2.30.0

07 Mar 17:42
@ruck314 ruck314
v2.30.0
22e978e
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Minor Release v2.30.0

Pull Requests Since v2.29.2

Unlabeled

  1. #960 - Adding support for non-Xilinx TCL build flow
  2. #959 - updating the ruckus.tcl to use non-symbolic link of proc.tcl
  3. #961 - Update SugoiSubordinateFsm.vhd

Pull Request Details

updating the ruckus.tcl to use non-symbolic link of proc.tcl
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Feb 28 08:52:55 2022 -0800
Pull: #959 (162 additions, 162 deletions, 162 files changed)
Branch: slaclab/ruckus_vivado_proc

Notes:

Description

  • In a future release of ruckus, I would like to get rid of this symbolic link to clean things up in that repo

Adding support for non-Xilinx TCL build flow
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Mar 4 16:35:20 2022 -0800
Pull: #960 (1103 additions, 354 deletions, 206 files changed)
Branch: slaclab/ruckus_synopsys_dc_support

Notes:

Description

  • Targetting Synposis Design Compiler as the non-Xilinx TCL build software
  • Synposis Design Compiler support added to ruckus at v4.2.0
  • Able to use the same ruckus.tcl files to load the source code for both Xilinx Vivado and Synposis Design Compiler
  • resolved some compilation errors from synposis

Update SugoiSubordinateFsm.vhd
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Mar 4 16:35:06 2022 -0800
Pull: #961 (15 additions, 0 deletions, 1 files changed)
Branch: slaclab/SugoiSubordinateFsm-path

Notes:

Description

  • Need to reset local AXI-Lite signals, state machine and counter during a global reset
  • Else the AXI-Lite might get out of "lock step" if the global reset happens during the middle of a AXI-Lite transaction
  • It is assumed that the global reset will be connected to all AXI-Lite end points's reset port in the device
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Patch Release v2.29.2

24 Feb 23:55
@ruck314 ruck314
v2.29.2
cbf4a90
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Patch Release v2.29.2

Pull Requests Since v2.29.1

Unlabeled

  1. #954 - SelectIoRxGearboxAligner: Expose the measured eyeWidth to userspace
  2. #955 - Renamed 'context' to 'ctx' due to VHDL2008 conflict
  3. #956 - microblaze vitis bug fix

Pull Request Details

SelectIoRxGearboxAligner: Expose the measured eyeWidth to userspace
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Feb 22 08:34:18 2022 -0800
Pull: #954 (58 additions, 11 deletions, 10 files changed)
Branch: slaclab/ESSURF-22
Jira: https://jira.slac.stanford.edu/issues/ESSURF-22

Notes:

Description

Renamed 'context' to 'ctx' due to VHDL2008 conflict
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Feb 22 08:34:07 2022 -0800
Pull: #955 (3 additions, 3 deletions, 2 files changed)
Branch: slaclab/vhdl2008-context

Notes:

Description

  • Breaks the SsiCmdMaster API ... but necessary if we use more VHDL2008 in the future
  • This will mostly impact older epix that need to upgrade their surf submodules

Context (VHDL 2008)

microblaze vitis bug fix
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Feb 24 13:28:50 2022 -0800
Pull: #956 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/microblaze-vitis-bug-fix

Notes:

Description

  • Removing leftovers from when surf use to support the SDK version (2019.1 and before)
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Patch Release v2.29.1

19 Feb 03:53
@ruck314 ruck314
v2.29.1
a7449db
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Patch Release v2.29.1

Pull Requests Since v2.29.0

Unlabeled

  1. #951 - adding CMOS support to SUGOI
  2. #952 - Sc18Is602Core update

Pull Request Details

adding CMOS support to SUGOI
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Feb 17 12:50:41 2022 -0800
Pull: #951 (74 additions, 38 deletions, 4 files changed)
Branch: slaclab/sugoi-cmos-support

Notes:

Description

  • Useful for short distance communication or need to reduce interconnect count

Sc18Is602Core update
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Feb 17 10:18:52 2022 -0800
Pull: #952 (3 additions, 3 deletions, 1 files changed)
Branch: slaclab/Sc18Is602Core-update
Issues: #950

Notes:

Description

  • reverting back to integer from positive due to maximum() function
  • related to #950
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Minor Release v2.29.0

15 Feb 23:54
@ruck314 ruck314
v2.29.0
a71444d
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Minor Release v2.29.0

Pull Requests Since v2.28.0

Unlabeled

  1. #946 - Adding SUGOI Protocol
  2. #950 - Update StdRtlPkg.vhd
  3. #1 - Jgt fixes to Gtx7CfgPkg.vhd
  4. #944 - Update Gearbox.vhd
  5. #945 - line-encoders bug fixes
  6. #948 - Update TenGigEthGthUltraScaleClk.vhd
  7. #935 - Changed getTKeep to return the number of bits set rather than the MSB+1
  8. #949 - Update I2cMuxPkg.vhd
  9. #942 - Fixed syntax error in AxiStreamPkg.vhd

Pull Request Details

Jgt fixes to Gtx7CfgPkg.vhd
Author: Gregg Thayer jgt@slac.stanford.edu
Date: Fri Feb 4 10:22:21 2022 -0800
Pull: #1 (27 additions, 19 deletions, 1 files changed)
Branch: ruck314/patch-1

Notes:

I split my fixes into two commits. The first is for the error condition asserts in getGtx7Cfg() and the other is to address the fact that the bit in QPLL_CFG_G that depends on the Vco band wasn't included in the configuration.

Changed getTKeep to return the number of bits set rather than the MSB+1
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Mon Feb 7 11:07:51 2022 -0800
Pull: #935 (6 additions, 1 deletions, 1 files changed)
Branch: lsst-camera-daq/lsst-tkeep

Notes:

The function getTKeep in AxiStreamPkg.vhd contains two branches based on the value of TKEEP_MODE.

When TKEEP_COUNT_C, then the function returns the largest number of bits that can be held by tKeep.

Otherwise, it returned the most significant set bit position +1. In other words a count of set bits that assumes that all bits below the MSB are also 1.

When the AxiStreamDmaWrite block counts the number of bytes transmitted, and tKeep violates this assumption data words are not written to memory. In my case, this can happen when the incoming PGP stream has transactions unaligned to 64-bit boundaries and tKeep can assume values like 0xC0, 0xF0, or 0xFC. Note when the alignment is in the other direction, tKeep of 0x03, 0x0F, and 0x3F will work with the current code.

AxiStreamDmaWrite is currently overriding the system TKEEP_MODE and setting it to TKEEP_NORMAL. It is unclear to me if some of the TKEEP_MODEs might actually want the current behavior of getTKeep.

Testing with this addition did not seem to adversely affect any of the LSST RCE uses of getTKeep, including the Ethernet PPI implementation. I suspect that in those cases, the assumption that the lower bits turns out to be true when actually counted.

Fixed syntax error in AxiStreamPkg.vhd
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Wed Feb 9 18:07:48 2022 -0800
Pull: #942 (2 additions, 1 deletions, 1 files changed)
Branch: slaclab/syntax-error-fix

Notes:

Description

  • Adding missing 'end if;'

Update Gearbox.vhd
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Feb 14 11:27:27 2022 -0800
Pull: #944 (9 additions, 5 deletions, 1 files changed)
Branch: slaclab/Gearbox-Updates

Notes:

Description

  • Migrated all the integer types to the appropriate natural and positive types
  • Adding wrap around when slip happens and writeIndex=0x0

line-encoders bug fixes
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Feb 14 09:47:23 2022 -0800
Pull: #945 (7 additions, 7 deletions, 3 files changed)
Branch: slaclab/Encoder-validIn-bug-fix

Notes:

Description

  • fixed bug where validIn was not implemented on any of the line-encoders
  • bug fix for Encoder8b10b and ASYNC reset

Adding SUGOI Protocol
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Feb 15 15:18:42 2022 -0800
Pull: #946 (2738 additions, 0 deletions, 14 files changed)
Branch: slaclab/sugoi-dev
Issues: #944, #945

Notes:

Description

Other Pull Request Dependence

Update TenGigEthGthUltraScaleClk.vhd
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Feb 15 10:42:17 2022 -0800
Pull: #948 (5 additions, 3 deletions, 1 files changed)
Branch: slaclab/ruck314-patch-1

Notes:

Description

  • Mapping theopen output ports to signals to get rid of ERROR: [VRFC 10-3628] partially associated formal error messages in simulation

Update I2cMuxPkg.vhd
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Feb 15 10:42:07 2022 -0800
Pull: #949 (6 additions, 0 deletions, 1 files changed)
Branch: slaclab/I2cMuxPkg-update

Notes:

Description

  • Adding decode table for PCA9546A

Update StdRtlPkg.vhd
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Feb 15 15:18:12 2022 -0800
Pull: #950 (0 additions, 58 deletions, 1 files changed)
Branch: slaclab/StdRtlPkg-revert
Issues: #936

Notes:

Description

  • Reverting back the changes from #936
  • I am getting VCS error messages (no error message in Vivado)

VCS Error Message Example

Warning-[XSYMTAB-CONFORM] Conformation violation detected
/u/re/ruckman/projects/fabulous-dev/firmware/submodules/surf/base/general/rtl/StdRtlPkg.vhd, 1203
STDRTLPKG

     function maximum (
              ^
  Subprogram header or deferred constant subtype indication does not conform
  to an earlier declaration.
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Minor Release v2.28.0

05 Feb 03:19
@ruck314 ruck314
v2.28.0
2cea96a
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Minor Release v2.28.0

Pull Requests Since v2.27.0

Unlabeled

  1. #938 - Release Candidate v2.28.0
  2. #936 - Adding devices/Nxp/SC18IS602BIPW Support and LMK python bug fix
  3. #932 - clean up and bug fixes for python/surf/devices/ti/Lmk
  4. #940 - adding AxiStreamFrameRateLimiter.vhd
  5. #939 - updates for RfDataConverter.py & RfTile.py
  6. #937 - ESROGUE-507: Fixed the slow AxiLiteMasterProxy module
  7. #933 - XPM_LIBRARIES bug fix for Vivado 2021.2 (and later)
  8. #941 - Fix clkFbIn drive when no BUFG
  9. #934 - Update LICENSE.txt

Pull Request Details

clean up and bug fixes for python/surf/devices/ti/Lmk
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Jan 24 08:49:57 2022 -0800
Pull: #932 (173 additions, 132 deletions, 3 files changed)
Branch: slaclab/LMK-python

Notes:

Description

  • Added simpleViewList support
  • LmkReg_0x0145, LmkReg_0x0171 and LmkReg_0x0172 are functionally different between Lmk04828 and Lmk04832. So moved out of the base python class
  • Added PLL1/2 Lock detect status registers
  • Bug fixes for LoadCodeLoaderHexFile()
  • Removed obsolete LoadCodeLoaderMacFile()
  • Bug fix for PwrDwnSysRef()

XPM_LIBRARIES bug fix for Vivado 2021.2 (and later)
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Feb 4 18:23:55 2022 -0800
Pull: #933 (10 additions, 0 deletions, 2 files changed)
Branch: slaclab/XPM_LIBRARIES

Notes:

Description

Update LICENSE.txt
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Thu Feb 3 16:41:12 2022 -0800
Pull: #934 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/ruck314-patch-1

Notes:

Description

  • Updating for year 2022

Adding devices/Nxp/SC18IS602BIPW Support and LMK python bug fix
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Feb 4 09:47:12 2022 -0800
Pull: #936 (627 additions, 21 deletions, 10 files changed)
Branch: slaclab/SC18IS602B

Notes:

Description

  • SC18IS602BIPW support
    • Implemented as a I2C-to-SPI memory mapped abstraction
    • No command or GPIO support
    • Required for communicating to the Xilinx CLK104 daughter board that's on most Xilinx RFSoC boards
  • Added PositiveArray and NaturalArray support to maximum() and minimum()
    • Required for the SC18IS602BIPW firmware implementation
  • Fixed namespace conflict with LMK Lmk04828.py and Lmk048base.py with respect to Init() function
  • bug fixes for Lmk04828 + LoadCodeLoaderHexFile()

ESROGUE-507: Fixed the slow AxiLiteMasterProxy module
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Wed Feb 2 14:41:51 2022 -0800
Pull: #937 (7 additions, 4 deletions, 1 files changed)
Branch: slaclab/esrogue-507

Notes:

Description

  • Add pollPeriod parameter for faster or slower polling for transaction
  • Set default pollPeriod to 0

Details

The AxiLiteMasterProxy kicks off a transaction and then polls a register for it to be done. It was enforcing a 0.1s sleep between each register poll, with at least one 0.1s sleep always happening. This slowed down access by quite a bit. This change allows the poll interval to be set with a parameter, with the default being no sleep at all.

JIRA

https://jira.slac.stanford.edu/browse/ESROGUE-507

Release Candidate v2.28.0
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Feb 4 19:15:19 2022 -0800
Pull: #938 (1148 additions, 179 deletions, 22 files changed)
Branch: slaclab/pre-release
Issues: #932, #937, #934, #936, #933, #939, #940, #941

Notes:

Description

updates for RfDataConverter.py & RfTile.py
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Feb 4 18:28:31 2022 -0800
Pull: #939 (58 additions, 29 deletions, 2 files changed)
Branch: slaclab/RfTile-py

Notes:

Description

  • fixed some of the variables with wrong 'mode'
  • polished the code to be cleaner for users that are new to RFSoC

adding AxiStreamFrameRateLimiter.vhd
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Feb 4 19:01:26 2022 -0800
Pull: #940 (280 additions, 0 deletions, 3 files changed)
Branch: slaclab/axis-frame-rate-throttle

Notes:

Description

  • Used for applications to set frame rate limit on a AXI stream
  • Typical use would preventing a large data stream from saturating the link and preventing configurations stream

Fix clkFbIn drive when no BUFG
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Feb 4 16:32:38 2022 -0800
Pull: #941 (2 additions, 2 deletions, 2 files changed)
Branch: slaclab/v2.26.0-clockmanagerfbin

Notes:

Description

  • Found that the clkFbIn pin was not being driven when generic FB_BUFG_G is False. Change:
    FbNoBufg : if (not FB_BUFG_G) generate
-      clkFbOut <= clkFbIn;
+      clkFbIn <= clkFbOut;
    end generate;
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Minor Release v2.27.0

11 Jan 23:27
@ruck314 ruck314
v2.27.0
56acb51
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Minor Release v2.27.0

Pull Requests Since v2.26.0

Enhancement

  1. #927 - adding Xilinx TMR python modules

Unlabeled

  1. #931 - Release Candidate v2.27.0
  2. #920 - FIR Filter Revamp
  3. #929 - AsyncGearbox.vhd Update
  4. #926 - AxiLiteCrossbar.vhd Update
  5. #925 - ICMP ping bug fix
  6. #930 - AxiSysMonUltraScale.py bug fix and a new feature

Pull Request Details

FIR Filter Revamp
Author: Benjamin Reese bengineerd@users.noreply.github.com
Date: Sat Dec 11 12:56:19 2021 -0800
Pull: #920 (283 additions, 321 deletions, 5 files changed)
Branch: slaclab/fir-filter-opt

Notes:

Description

This PR makes several changes to the FIR Filter modules.

  • The DSP48 internal register and enable are used for pipeline stalls, rather than external registers and logic.
  • Different coefficient and data widths are now allowed.
  • MultiChannelFirFilter now only allows one set of coefficients to be applied to all channels.
    • The logic allowing different coefficients per channel was broken.
    • Fixing it would require extensive changes to AxiDualPortRam
  • Coefficients now held in AxiDualPortRam with shadow registers for parallel read.
    • Seems counterintuitive, but ends up saving resources.
    • Use AxiDualPortRam to handle AXI address decode and read muxing.
    • Shadow registers allow all coefficients to be accessed in parallel for filter application.
    • Also allows for easy synchronization between AXI-Lite clock and data clock.
  • FirFilterSingleChannel now has sideband interface.
    • Allows sideband data to get same pipeline delay as the filter.
  • Some generic names have been updated for clarity.
    • OK since nothing was using these modules yet.
  • Software
    • Use Fixed type variables
      • Automatically converts floats to internal fixed point representation.
    • Use array variables
      • Allows all coefficients to be accessed in a single SRP transaction.

ICMP ping bug fix
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Nov 30 15:07:53 2021 -0700
Pull: #925 (11 additions, 5 deletions, 1 files changed)
Branch: slaclab/icmp-ping-bug-fix

Notes:

Description

  • Happened when request checksum >= 0xF800
  • Bug report by Antonio abergnol@cern.ch

AxiLiteCrossbar.vhd Update
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Sun Dec 12 10:49:57 2021 -0800
Pull: #926 (12 additions, 7 deletions, 1 files changed)
Branch: slaclab/ESSURF-18
Jira: https://jira.slac.stanford.edu/issues/ESSURF-18

Notes:

Description

  • Resolved NULL assignment critical warning message when 32-bit MUX

adding Xilinx TMR python modules
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Jan 3 16:22:41 2022 -0800
Pull: #927 (301 additions, 1 deletions, 4 files changed)
Branch: slaclab/TmrSem
Labels: enhancement

Notes:

Description

  • Adding TMR controller, TMR inject and TMR SEM python register mapping

AsyncGearbox.vhd Update
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Jan 7 12:00:00 2022 -0800
Pull: #929 (31 additions, 27 deletions, 1 files changed)
Branch: slaclab/AsyncGearbox-perf-opt

Notes:

Description

  • adding EN_EXT_CTRL_G to help with optimizing the synchronizers when unused

AxiSysMonUltraScale.py bug fix and a new feature
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Jan 10 09:21:22 2022 -0800
Pull: #930 (7 additions, 4 deletions, 1 files changed)
Branch: slaclab/AxiSysMonUltraScale

Notes:

Description

  • VP_VN should use the convAuxVoltage() function instead of convCoreVoltage() function
  • I have confirmed this in real hardware and confirmed that value now matches what JTAG viewer shows
  • new arg for customizing the simpleView

Release Candidate v2.27.0
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Jan 11 15:22:29 2022 -0800
Pull: #931 (645 additions, 365 deletions, 13 files changed)
Branch: slaclab/pre-release
Issues: #925, #920, #926, #927, #929, #930

Notes:

Description

Contributors

slacrherbst
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Minor Release v2.26.0

20 Nov 00:46
@ruck314 ruck314
v2.26.0
ff4ebd7
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Minor Release v2.26.0

Pull Requests Since v2.25.2

Unlabeled

  1. #924 - Release Candidate v2.26.0
  2. #923 - adding HSkip, HActive, VSkip, VActive to CLINK

Pull Request Details

adding HSkip, HActive, VSkip, VActive to CLINK
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Nov 19 16:39:51 2021 -0800
Pull: #923 (132 additions, 20 deletions, 4 files changed)
Branch: slaclab/clink-inactive-pixel-skip-support

Notes:

Description

  • Required for supporting the U900 camera
    • Where the raw camera image size (active and inactive pixels) are not the same for all cameras

Release Candidate v2.26.0
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Nov 19 16:41:20 2021 -0800
Pull: #924 (132 additions, 20 deletions, 4 files changed)
Branch: slaclab/pre-release
Issues: #923

Notes:

Description

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Patch Release v2.25.2

18 Nov 23:55
@ruck314 ruck314
v2.25.2
9e601c6
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Patch Release v2.25.2

Pull Requests Since v2.25.1

Unlabeled

  1. #922 - Release Candidate v2.25.2
  2. #912 - MicroblazeBasicCore + Vivado 2021.2 bug fix
  3. #921 - Bug fixes for UartRx and Clink
  4. #915 - Use DSP Clock Enable to Stall Filter Pipeline
  5. #919 - Show hex and ascii in UP900 serial diagnostics
  6. #913 - Fix AxiStreamTap
  7. #917 - Pre release axistreamtap: fix type in MODE_G = PASSTRHOUGH
  8. #914 - ESSURF-20 - AxiStreamTap Mux Mode Fix

Pull Request Details

MicroblazeBasicCore + Vivado 2021.2 bug fix
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Nov 1 12:50:15 2021 -0700
Pull: #912 (1654 additions, 468 deletions, 3 files changed)
Branch: slaclab/microblaze-2021.2

Notes:

Description

  • Required for resolving a .bd module version locking issue

Fix AxiStreamTap
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Nov 3 13:36:31 2021 -0700
Pull: #913 (10 additions, 10 deletions, 1 files changed)
Branch: slaclab/essurf-19

Notes:

Description

AxiStreamDemux now evaluates routes from low index to high index. This broke AxiStreamTap as everything was being routed to index 0.

Details

JIRA

https://jira.slac.stanford.edu/browse/ESSURF-19

Related

ESSURF-20 - AxiStreamTap Mux Mode Fix
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Nov 4 12:47:32 2021 -0700
Pull: #914 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/essurf-20

Notes:

Description

The output mux now uses MODE_G => "PASSTHROUGH" so as not to modify the incoming TDESTs.

JIRA

https://jira.slac.stanford.edu/browse/ESSURF-20

Related

Use DSP Clock Enable to Stall Filter Pipeline
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Mon Nov 8 16:06:51 2021 -0800
Pull: #915 (20 additions, 27 deletions, 2 files changed)
Branch: slaclab/fir-filter-opt

Notes:

Description

This change makes use the the DSP48 clock enable signal to stall the pipeline on cycles when it should not advance.

Previously, the design was synthesizing a set of stall registers and associated logic between each filter stage. Now it synthesizes a string of DSP48 blocks with no glue logic in between to create the filter.

Pre release axistreamtap: fix type in MODE_G = PASSTRHOUGH
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Nov 9 08:35:47 2021 -0800
Pull: #917 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/pre-release-axistreamtap

Notes:

Description

AxiStreamTap.vhd U_MUX : MODE_G => "PASSTRHOUGH" becomes "PASSTHROUGH"

Show hex and ascii in UP900 serial diagnostics
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Nov 16 19:47:37 2021 -0800
Pull: #919 (18 additions, 4 deletions, 1 files changed)
Branch: bhill-slac/Up900-diags

Notes:

Description

  • Show both hex and ascii output in UP900 serial diagnostics.

Bug fixes for UartRx and Clink
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Nov 18 15:06:15 2021 -0800
Pull: #921 (319 additions, 85 deletions, 7 files changed)
Branch: slaclab/clink-dev

Notes:

Description

  • Fixed broken ClinkFramerTb simulation test bench
  • Added ClinkUartTb simulation test bench
  • bug fix to UartRx.vhd
  • bug fix to ClinkPkg.vhd
  • adding frameSize register to ClinkReg

Release Candidate v2.25.2
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Nov 18 15:49:32 2021 -0800
Pull: #922 (2022 additions, 595 deletions, 14 files changed)
Branch: slaclab/pre-release
Issues: #912, #913, #914, #915, #917, #919, #921

Notes:

Description

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Patch Release v2.25.1

27 Oct 19:42
@ruck314 ruck314
v2.25.1
a8b3b33
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Patch Release v2.25.1

Pull Requests Since v2.25.0

Unlabeled

  1. #911 - Release Candidate v2.25.1
  2. #909 - Vivado Version check for FIFO XPM
  3. #910 - Fix variable.get(read) calls for Rogue 5.11

Pull Request Details

Vivado Version check for FIFO XPM
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Tue Oct 26 10:11:40 2021 -0700
Pull: #909 (21 additions, 5 deletions, 4 files changed)
Branch: slaclab/xpm-legacy-vivado

Notes:

Description

  • use xpm.vcomponents.all; does not exist for older versions of Vivado
  • Loading the "dummy" version of the VHDL XPM prevents "VHDL library does not exist" error message
    • Added an assert to the dummy module to prevent it from being "accidentally" compiled

Fix variable.get(read) calls for Rogue 5.11
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Oct 27 11:01:27 2021 -0700
Pull: #910 (4 additions, 4 deletions, 2 files changed)
Branch: slaclab/rogue-5.11-fix

Notes:

Description

The read parameter to variable.get() is now a keyword-only argument as of Rogue 5.11. I have fixed all calls that were passing it by position.

Release Candidate v2.25.1
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Oct 27 12:38:02 2021 -0700
Pull: #911 (25 additions, 9 deletions, 6 files changed)
Branch: slaclab/pre-release
Issues: #909, #910

Notes:

Description

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Minor Release v2.25.0

22 Oct 17:49
@ruck314 ruck314
v2.25.0
8caa69a
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Minor Release v2.25.0

Pull Requests Since v2.24.3

Unlabeled

  1. #906 - Release Candidate v2.25.0
  2. #907 - Add priority generic to AxiStreamMux
  3. #908 - Update to SspLowSpeedDecoderReg
  4. #905 - increasing ethernet/TenGigEthCore PwrUpRst from 100ms to 1000ms
  5. #904 - Prepare for numpy list updates in Rogue

Pull Request Details

Prepare for numpy list updates in Rogue
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Wed Oct 6 07:25:16 2021 -0700
Pull: #904 (14 additions, 5 deletions, 3 files changed)
Branch: slaclab/np_update

Notes:

This PR prepares a few modules in SURF for an upcoming update to Rogue. This upcoming Rogue change update replaces the use of lists for bulk writes to variables with numpy arrays. The changes made to this file are backward compatible with both the current version of Rogue and the future upgrade of Rogue.

Backwards compatibility is accomplished by reading back the current variable data with read = False. In the old version of Rogue this will return a list. In the new version this will return a numpy array.

increasing ethernet/TenGigEthCore PwrUpRst from 100ms to 1000ms
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Oct 21 14:00:15 2021 -0700
Pull: #905 (23 additions, 23 deletions, 5 files changed)
Branch: slaclab/TenGigEthCore-PwrUpRst

Notes:

Description

  • We have found empirically that 100ms is sometimes too short at power up and the ETH phy ready does not come up
  • Increasing the power up reset duration seems to make the ETH PHY ready come up everytime now

Release Candidate v2.25.0
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Fri Oct 22 10:44:53 2021 -0700
Pull: #906 (155 additions, 98 deletions, 15 files changed)
Branch: slaclab/pre-release
Issues: #904, #905, #907, #908

Notes:

Description

Add priority generic to AxiStreamMux
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Oct 21 15:56:20 2021 -0700
Pull: #907 (81 additions, 52 deletions, 2 files changed)
Branch: slaclab/priority-mux
Issues: #44, #45

Notes:

Description

This change allows AxiStreamMux to give priority to specific input streams rather than pure round-robin arbitration.

Details

The PRIORITY_G generic allows each input stream index to be given a priority value. Input streams with higher priority will always be selected over those with lower priority when both are active.

In the below example, channel 2 has the highest priority value, so it will always be selected over the others when trying to push data through the mux. Channel 0 has the next highest priority. It will be selected over channels 1 and 3 if all channels are active at once. Channels 1 and 3 have the lowest priority, and effectively share round robin access with each other when channels 0 and 2 are not active.

      U_AxiStreamMux_DATA : entity surf.AxiStreamMux
         generic map (
            TPD_G                => TPD_G,
            NUM_SLAVES_G         => RSSI_ROUTES_C'length,
            MODE_G               => "ROUTED",
            TDEST_ROUTES_G       => RSSI_ROUTES_C,
            PRIORITY_G                => (
               0  => 1,
               1  => 0,
               2 => 2,
               3 => 0),
            ILEAVE_EN_G          => true,
            ILEAVE_ON_NOTVALID_G => true,
            ILEAVE_REARB_G       => (512/8)-3)
         port map (
            axisClk      => ethClk,                                  -- [in]
            axisRst      => ethRst,                                  -- [in]
            sAxisMasters => dataRssiIbMasters,                       -- [in]
            sAxisSlaves  => dataRssiIbSlaves,                        -- [out]
            mAxisMaster  => rogueMuxAxisMasters(DATA_RSSI_INDEX_C),  -- [out]
            mAxisSlave   => rogueMuxAxisSlaves(DATA_RSSI_INDEX_C));  -- [in]

Backward compatibility

This is fully backward compatible. If PRIORITY_G is not set, the default is unchanged - all streams have equal priority.

RSSI

RssiCoreWrapper now has an APP_STREAM_PRIORITY_G generic that is passed to PRIORITY_G of the internal mux. This allows RSSI app streams to be given outgoing priority.

Update to SspLowSpeedDecoderReg
Author: Larry Ruckman ruckman@slac.stanford.edu
Date: Thu Oct 21 13:28:59 2021 -0700
Pull: #908 (37 additions, 18 deletions, 5 files changed)
Branch: slaclab/SelectIoRxGearboxAligner-update

Notes:

Description

  • Changing UsrDlyCfg from being a "common" register for all lanes to an register array (1 per lane)
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